小梅哥FPGA(4)---线性序列机原理与应用

1、任务一

代码：

2、任务二

这里为了简单只是观察一下现象，我们这个用2:4:6:8来进行

module led_flash(
    input clk,
    input Reset,
    output reg led
);

parameter Max1=1;
parameter Max2=5;
parameter Max3=11;
parameter Max4=19;

reg [6:0] cnt;

always@(posedge clk or negedge Reset) begin
    if(!Reset)
        cnt<=0;
    else if(cnt==Max4)
        cnt<=0;
    else
        cnt<=cnt+1'b1;
end

always@(posedge clk or negedge Reset) begin
    if(!Reset)
        led<=1;
    else if(cnt==Max1)
        led<=0;
    else if(cnt==Max2)
        led<=1;
    else if(cnt==Max3)
        led<=0;
    else if(cnt==Max4)
        led<=1;
    else    
        led<=led;
end


endmodule

testbench:

`timescale 1ns/1ns


module led_flash_tb();

reg clk;
reg Reset;
wire led;

always #10 clk=~clk;

initial begin
    clk=1;
    Reset=0;
    #25
    Reset=1;
    #2000
    $stop;
end

led_flash inst(
    .clk(clk),
    .Reset(Reset),
    .led(led)
);

endmodule

新的实现思路：我们可以观察到时间间隔都是0.25的整数倍，然后从之前的每一个时钟脉冲counter加一转换成了0.25s的时候counter加一。

3、下面这个思想很重要哈

module led_flash(
    input clk,
    input Reset,
    output reg led
);

parameter MCNT= 12_500_000-1;


reg [23:0] cnt;
reg [3:0] counter1;

always@(posedge clk or negedge Reset) begin
    if(!Reset)
        cnt<=0;
    else if(cnt==MCNT)
        cnt<=0;
    else
        cnt<=cnt+1'b1;
end

always@(posedge clk or negedge Reset) begin
    if(!Reset)
        counter1<=0;
    else if(cnt==MCNT) begin
        if(counter1==9)
            counter1<=0;
        else
            counter1<=counter1+1'b1;
    end
        
    else
        counter1<=counter1;
end


always@(posedge clk or negedge Reset) begin
    if(!Reset)
        led<=0;
    else begin
        case(counter1)     //这里的LED是慢了一拍的哈，可以根据图像去解释他
            0:led<=1'd1;
            1:led<=1'd0;
            2:led<=1'd0;
            3:led<=1'd1;
            4:led<=1'd1;
            5:led<=1'd1;
            6:led<=1'd0;
            7:led<=1'd0;
            8:led<=1'd0;
            9:led<=1'd0;
            default:led<=led;            
        endcase
    end
end


endmodule

tesetbench:

`timescale 1ns/1ns


module led_flash_tb();

reg clk;
reg Reset;
wire led;

always #10 clk=~clk;

initial begin
    clk=1;
    Reset=0;
    #25
    Reset=1;
    #3000000000;
    $stop;
end

led_flash inst(
    .clk(clk),
    .Reset(Reset),
    .led(led)
);

endmodule

但是要记住这里稍微慢了一拍，就是时钟

4、任务3

LED的状态不再跟之前那样子是已知的了，是需要用户确定的,也就是输入端口可以不断发生变化的意思

module led_flash(
    input clk,
    input rst_n,
    input [7:0] SW,  //这里是拨码开关
    output reg led
);

parameter MCNT=12_500_000;
reg [23:0] cnt;
reg [3:0] counter1;

always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cnt<=0;
    else if(cnt==MCNT)
        cnt<=0;
    else
        cnt<=cnt+1'b1;
end


always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        counter1<=0;
    else if(cnt==MCNT) begin
        if(counter1==7)
            counter1<=0;
        else
            counter1<=counter1+1;
    end
    else
        counter1<=counter1;
end

always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        led<=0;
    else begin
        case(counter1)     //这里的LED是慢了一拍的哈，可以根据图像去解释他
            0:led<=SW[0];
            1:led<=SW[1];
            2:led<=SW[2];
            3:led<=SW[3];
            4:led<=SW[4];
            5:led<=SW[5];
            6:led<=SW[6];
            7:led<=SW[7];
            default:led<=led;
        endcase
    end
end

endmodule

5、任务4