摘要：Note: Do not compile any Altera model files that are located in the quartus/eda/sim_lib directory. Note: VHDL logical libraries have the names listed in the table. VHDL logical libraries have a _ver suffix. Logical Library NameLibrary DescriptionarriagxArriaGXarriagx_hssiArriaGX devices with tra... 阅读全文