ZYNQ UltraScale uboot SGMII network port debugging TFTP 88E1111

原始链接https://www.programmersought.com/article/10824313113/

 

ZYNQ UltraScale uboot SGMII network port debugging TFTP

tags: ZYNQ Ultrascale + MPSoc  ZYNQ development  linux  Embedded

 
 

ZYNQ UltraScale uboot SGMII network port debugging

1. Software and hardware platform

ＺYNQ Ultrascale　MPSOC XCZU19EGFFVC1760
Petalinux　2019.1

I use petalinux2019.1 during the uboot phase, the network port is unreachable, and the kernel can communicate normally.

2. Hardware circuit design # 3. uboot　 debugging notes

3.1 Uboot device tree and its local source path configuration

  1.  
    The device tree used by default on this platform is uboot
  2.  
    zynqmp-zcu102.rev1.0.dts
  3.  
    zynqmp-zcu102.revA.dts
  4.  
    zynqmp-zcu102.revB.dts

The source code is located at:
/opt/pkg/source_code/u-boot-xlnx-master/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
The uboot source code is difficult to find under Petalinux. You can go to xilinx official download the relevant source code
Xilinx source official git:
link:link.
petalinux-config
## 2. Uboot network card source code analysis
Source code path:
/opt/pkg/source_code/u-boot-xlnx-master/drivers/net/zynq_gem.c
After the system starts, FSBL->Uboot
Use zynq_gem_ofdata_to_platdata() to obtain information about the related nodes of the device tree:
For example: phy-handle
　reg
　max-speed
　phy-mode
#### #####:
The initial debugging is to modify the device tree file under the uboot source code, and configure gem0 as the default network debugging port:
is as follows:
file: zynqmp-zcu102.revA.dts

  1.  
    aliases {
  2.  
    ethernet0 = &gem0; //kuens
  3.  
    gpio0 = &gpio;
  4.  
    i2c0 = &i2c0;
  5.  
    i2c1 = &i2c1;
  6.  
    mmc0 = &sdhci1;
  7.  
    rtc0 = &rtc;
  8.  
    serial0 = &uart0;
  9.  
    serial1 = &uart1;
  10.  
    serial2 = &dcc;
  11.  
    spi0 = &qspi;
  12.  
    //usb0 = &usb0;
  13.  
    };
	file:zynqmp-zcu102.revB.dts
  1.  
    //kuens
  2.  
    &gem0{
  3.  
    local-mac-address = [00 40 85 44 00 E0];
  4.  
    status = "okay";
  5.  
    //is-internal-pcspma = <0x1>;
  6.  
    phy-handle = <&phy3>;
  7.  
    phy-mode = "sgmii";
  8.  
    //pinctrl-names = "default";
  9.  
     
  10.  
    mdio {
  11.  
    #address-cells = <0x1>;
  12.  
    #size-cells = <0x0>;
  13.  
    phy3: phy@3 {
  14.  
    compatible = "marvell,88e1111";
  15.  
    device_type = "ethernet-phy";
  16.  
    reg = <3>;
  17.  
    //linux,phandle = <0x4>;
  18.  
    //phandle = <0x4>;
  19.  
    };
  20.  
    };
  21.  
    };

As shown in the figure above, there is no abnormal configuration, but the communication is abnormal during the uboot stage, showing an ARP error.

3.1 NIC initialization process

  1.  
    zynq_gem_probe(struct udevice *dev) function:
  2.  
    //Allocate space for tx_bd rx_bd
  3.  
    priv->tx_bd = (struct emac_bd *)bd_space;
  4.  
    priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
  5.  
    //Assign mdio　bus
  6.  
    priv->bus = mdio_alloc();
  7.  
    //Initialize 　read and write function
  8.  
    priv->bus->read = zynq_gem_miiphy_read;
  9.  
    priv->bus->write = zynq_gem_miiphy_write;
  10.  
    //Register
  11.  
    ret = mdio_register(priv->bus);
  12.  
    return zynq_phy_init(dev);
  13.  
     
  14.  
    zynq_phy_init(struct udevice *dev) function:
  15.  
    writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
  16.  
    ret = phy_detection(dev);
  17.  
    priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,priv->interface);

//View definition
#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
Mainly initialize the gem register, and then configure phy through mdio
zynq_gem_init() function analysis:

  1.  
    /* Device registers */
  2.  
    struct zynq_gem_regs {
  3.  
    u32 nwctrl; /* 0x0 - Network Control reg */
  4.  
    u32 nwcfg; /* 0x4 - Network Config reg */
  5.  
    u32 nwsr; /* 0x8 - Network Status reg */
  6.  
    u32 reserved1;
  7.  
    u32 dmacr; /* 0x10 - DMA Control reg */
  8.  
    u32 txsr; /* 0x14 - TX Status reg */
  9.  
    u32 rxqbase; /* 0x18 - RX Q Base address reg */
  10.  
    u32 txqbase; /* 0x1c - TX Q Base address reg */
  11.  
    u32 rxsr; /* 0x20 - RX Status reg */
  12.  
    u32 reserved2[2];
  13.  
    u32 idr; /* 0x2c - Interrupt Disable reg */
  14.  
    u32 reserved3;
  15.  
    u32 phymntnc; /* 0x34 - Phy Maintaince reg */
  16.  
    u32 reserved4[18];
  17.  
    u32 hashl; /* 0x80 - Hash Low address reg */
  18.  
    u32 hashh; /* 0x84 - Hash High address reg */
  19.  
    #define LADDR_LOW 0
  20.  
    #define LADDR_HIGH 1
  21.  
    u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
  22.  
    u32 match[4]; /* 0xa8 - Type ID1 Match reg */
  23.  
    u32 reserved6[18];
  24.  
    #define STAT_SIZE 44
  25.  
    u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
  26.  
    u32 reserved9[20];
  27.  
    u32 pcscntrl;
  28.  
    u32 rserved12[36];
  29.  
    u32 dcfg6; /* 0x294 Design config reg6 */
  30.  
    u32 reserved7[106];
  31.  
    u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
  32.  
    u32 reserved8[15];
  33.  
    u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
  34.  
    u32 reserved10[17];
  35.  
    u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
  36.  
    u32 reserved11[2];
  37.  
    u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
  38.  
    };
	This structure is related to the definition of the gem register.

Note part:
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH |
ZYNQ_GEM_NWCFG_FDEN |
ZYNQ_GEM_NWCFG_FSREM |
ZYNQ_GEM_NWCFG_MDCCLKDIV)
nwconfig = ZYNQ_GEM_NWCFG_INIT;

  1.  
    /*
  2.  
    * Set SGMII enable PCS selection only if internal PCS/PMA
  3.  
    * core is used and interface is SGMII.
  4.  
    */
  5.  
    if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
  6.  
    priv->int_pcs) {
  7.  
    nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
  8.  
    ZYNQ_GEM_NWCFG_PCS_SEL;
  9.  
    #ifdef CONFIG_ARM64
  10.  
    writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
  11.  
    &regs->pcscntrl);
  12.  
    #endif
  13.  
    }

The device tree is configured in SGMII mode:

According to the register definition, register 0xFF0B0004 bit27 is 1
Start uboot and use the md command to read the register parameters:
md instruction usage:
Entering the command md under uboot will prompt the usage of md, memory display, which is memory display.
U-Boot-PetaLinux> md
md - memory display
Usage:
md [.b, .w, .l] address [# of objects]
b: 8 bits
w: 16 bits
l: 32 bits (default value)
For example:

Set the server ip:
ZynqMP> print serverip
ZynqMP> set serverip ; saveenv
start:
ZynqMP> run netboot
Summary: It is recommended not to modify the device tree under the source path in the device tree modification. Including: the device tree under uboot and kernel, suggest to modify
system-user.dtsi
Reference:
ug1144.pdf
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

 

posted on 2021-03-17 11:46  Kevin_HeYongyuan  阅读(855)  评论(0)    收藏  举报

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