VGA的相关代码

一、RTL视图

二、

module sync_module(
input VGA_CLK,  //800x600
input RST_N,
output VGA_HS,VGA_VS,valid,
output[10:0] X,Y    //column and row addr signal
);
 
reg[10:0] Count_H;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        Count_H<=11'd0;
    else if(Count_H==11'd1056)
        Count_H<=11'd0;
    else
        Count_H<=Count_H+1'b1;
 
reg[10:0] Count_V;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        Count_V<=11'd0;
    else if(Count_V==11'd628)
        Count_V<=11'd0;
    else if(Count_H==11'd1056)
        Count_V<=Count_V+1'b1;
       
reg valid_r;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        valid_r<=1'b0;
    else if((Count_H>216&&Count_H<1017)&&(Count_V>11'd27&&Count_V<11'd627))
        valid_r<=1'b1;
    else
        valid_r<=1'b0;
       
assign VGA_HS=(Count_H<=11'd128) ? 1'b0 : 1'b1;
assign VGA_VS=(Count_V<=11'd4) ? 1'b0 : 1'b1;
assign valid=valid_r;
 
assign X=valid_r ? Count_H-11'd217 : 11'd0;
assign Y=valid_r ? Count_V-11'd28 : 11'd0;
 
endmodule

vga_control_module

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module vga_control_module(
input VGA_CLK,
input RST_N,
input[10:0] X,Y,
input valid,
output[7:0] VGA_R,VGA_G,VGA_B
);
 
reg rectangle;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        rectangle<=1'b0;
    //else if(X>11'd0&&Y<11'd100)
    else if((X>11'd0&&X<11'd100)||(X>11'd700&&X<11'd800)||(Y>11'd0&&Y<11'd100)||(Y>11'd500&&Y<11'd600))
        rectangle<=1'b1;
    else
        rectangle<=1'b0;
 
assign VGA_R=valid&&rectangle ? 8'b1111_1111 : 8'b0;
assign VGA_G=valid&&rectangle ? 8'b1111_1111 : 8'b0;
assign VGA_B=valid&&rectangle ? 8'b1111_1111 : 8'b0;
 
endmodule
vga_module
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//* Display a rectangle
module vga_module(
input CLOCK_50,
input[3:0] KEY,
output VGA_CLK,
output[7:0] VGA_R,VGA_G,VGA_B,
output VGA_HS,VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N
);
 
assign VGA_SYNC_N=1'b0; //If not SOG,Sync input should be tied to 0;
assign VGA_BLANK_N=VGA_HS&&VGA_VS;
 
pll_module u1(
                .inclk0 ( CLOCK_50 ),
                .c0 ( VGA_CLK ) //VGA_CLK=CLK_40=1056x628x60;
                );
 
wire[10:0] X,Y;
wire valid;
 
wire RST_N;
assign RST_N=KEY[0];
sync_module u2(
                .VGA_CLK(VGA_CLK),
                .RST_N(RST_N),
                .VGA_HS(VGA_HS),
                .VGA_VS(VGA_VS),
                .X(X),
                .Y(Y),
                .valid(valid)
                );
vga_control_module u3(
                        .VGA_CLK(VGA_CLK),
                        .RST_N(RST_N),
                        .VGA_R(VGA_R),
                        .VGA_G(VGA_G),
                        .VGA_B(VGA_B),
                        .X(X),
                        .Y(Y),
                        .valid(valid)
                        );
endmodule

sync_module

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module vga_module(
input CLOCK_50,
input[3:0] KEY,
output VGA_CLK,
output[7:0] VGA_R,VGA_G,VGA_B,
output VGA_HS,VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N
);
 
assign VGA_SYNC_N=1'b0; //If not SOG,Sync input should be tied to 0;
assign VGA_BLANK_N=VGA_HS&&VGA_VS;
 
pll_module u1(
                .inclk0 ( CLOCK_50 ),
                .c0 ( VGA_CLK )
                );
 
wire[10:0] X,Y;
wire valid;
 
wire RST_N;
assign RST_N=KEY[0];
sync_module u2(
                .VGA_CLK(VGA_CLK),
                .RST_N(RST_N),
                .VGA_HS(VGA_HS),
                .VGA_VS(VGA_VS),
                .X(X),
                .Y(Y),
                .valid(valid)
                );
               
wire[63:0] Rom_Data;
wire[5:0] Rom_Addr;
rom_module u4(
                .clock(VGA_CLK),
                .address(Rom_Addr),
                .q(Rom_Data)
                );
               
vga_control_module u3(
                        .VGA_CLK(VGA_CLK),
                        .RST_N(RST_N),
                        .VGA_R(VGA_R),
                        .VGA_G(VGA_G),
                        .VGA_B(VGA_B),
                        .X(X),
                        .Y(Y),
                        .valid(valid),
                        .Rom_Addr(Rom_Addr),
                        .Rom_Data(Rom_Data)
                        );
endmodule

vga_control_module

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module vga_control_module(
input VGA_CLK,
input RST_N,
input[10:0] X,Y,
input valid,
input[63:0] Rom_Data,
output[5:0] Rom_Addr,
output[7:0] VGA_R,VGA_G,VGA_B
);
 
reg[5:0] m;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        m<=6'b0;
    else if(valid && Y<64)
        m<=Y[5:0];
       
reg[5:0] n;
always@(posedge VGA_CLK or negedge RST_N)
    if(!RST_N)
        n<=6'b0;
    else if(valid && X<64)
        n<=X[5:0];
 
assign Rom_Addr=m;
 
assign VGA_R=valid ? {Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n]} : 8'b0;
assign VGA_G=valid ? {Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n]} : 8'b0;
assign VGA_B=valid ? {Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n],Rom_Data[6'd63-n]} : 8'b0;
       
endmodule
vga_module
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//* Display a photo pika.bmp(64x64)
module vga_module(
input CLOCK_50,
input[3:0] KEY,
output VGA_CLK,
output[7:0] VGA_R,VGA_G,VGA_B,
output VGA_HS,VGA_VS,
output VGA_BLANK_N,
output VGA_SYNC_N
);
 
assign VGA_SYNC_N=1'b0; //If not SOG,Sync input should be tied to 0;
assign VGA_BLANK_N=VGA_HS&&VGA_VS;
 
pll_module u1(
                .inclk0 ( CLOCK_50 ),
                .c0 ( VGA_CLK )
                );
 
wire[10:0] X,Y;
wire valid;
 
wire RST_N;
assign RST_N=KEY[0];
sync_module u2(
                .VGA_CLK(VGA_CLK),
                .RST_N(RST_N),
                .VGA_HS(VGA_HS),
                .VGA_VS(VGA_VS),
                .X(X),
                .Y(Y),
                .valid(valid)
                );
               
wire[63:0] Rom_Data;
wire[5:0] Rom_Addr;
rom_module u4(
                .clock(VGA_CLK),
                .address(Rom_Addr),
                .q(Rom_Data)
                );
               
vga_control_module u3(
                        .VGA_CLK(VGA_CLK),
                        .RST_N(RST_N),
                        .VGA_R(VGA_R),
                        .VGA_G(VGA_G),
                        .VGA_B(VGA_B),
                        .X(X),
                        .Y(Y),
                        .valid(valid),
                        .Rom_Addr(Rom_Addr),
                        .Rom_Data(Rom_Data)
                        );
endmodule

posted on 2013-01-12 10:52  不灭的流星  阅读(280)  评论(0)    收藏  举报

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