随笔分类 -  Hdlbits的Verilog学习

摘要:Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0 阅读全文
posted @ 2024-04-10 01:59 江左子固 阅读(75) 评论(0) 推荐(0)
摘要:Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the count 阅读全文
posted @ 2024-04-10 01:53 江左子固 阅读(83) 评论(0) 推荐(0)