mux and dff(1)

Taken from ECE253 2015 midterm question 5

Consider the sequential circuit below:

Mt2015 muxdff - HDLBits (01xz.net)

 

module top_module (
    input clk,
    input L,
    input r_in,
    input q_in,
    output reg Q);
always @(posedge clk) begin
        Q <= L?r_in:q_in;
    end
endmodule