conditional ternary operator

Verilog has a ternary conditional operator ( ? : ) much like C:

(condition ? if_true : if_false)

This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational always block.

Conditional - HDLBits (01xz.net)

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//
 assign min = (a<b) ? 
        ((a<c) ? ((a<d) ? a:d) : ((c<d)? c:d)):
        ((b<c) ? ((b<d) ? b:d) : ((c<d)?c:d));
//没看懂
    // assign intermediate_result1 = compare? true: false;

endmodule

 再写：

怎么说呢，这种多嵌套的三目运算写是没啥问题，但是容易晕

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//
    wire [7:0]m1;
    wire [7:0]m2;
    assign m1=(a>b)?b:a;
    assign m2=(m1>c)?c:m1;
    assign min=(m2>d)?d:m2;
    // assign intermediate_result1 = compare? true: false;

endmodule