avoiding latches

Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

Always nolatches - HDLBits (01xz.net)

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
always @(*)begin
        left<=1'b0;down<=1'b0;right<=1'b0;up<=1'b0;
        case(scancode)
            16'he06b:left<=1'b1;  
            16'he072:down<=1'b1;
            16'he074:right<=1'b1;
            16'he075:up<=1'b1;
            default:begin
                left<=1'b0;down<=1'b0;right<=1'b0;up<=1'b0;
            end
        endcase   
    end

endmodule

 再写：

说明一下16'HE06B，因为Scancode是一个16位的数值，所以在这里简化表达，用十六进制来书写了

另外，对应之前latch部分的思考，为了避免不必要的latch的产生，需要在case中为没有赋值的状态书写default

二、8【FPGA】Verilog中锁存器（Latch）原理、危害及避免_verilog latch-CSDN博客