case statement 

Case statements in Verilog are nearly equivalent to a sequence of if-elseif-else that compares one expression to a list of others. Its syntax and functionality differs from the switch statement in C.

Always case - HDLBits (01xz.net)

 1 // synthesis verilog_input_version verilog_2001
 2 module top_module ( 
 3     input [2:0] sel, 
 4     input [3:0] data0,
 5     input [3:0] data1,
 6     input [3:0] data2,
 7     input [3:0] data3,
 8     input [3:0] data4,
 9     input [3:0] data5,
10     output reg [3:0] out   );//
11 
12     always@(*) begin  // This is a combinational circuit
13         case(sel)
14              3'd0:out<=data0;
15              3'd1:out<=data1;
16              3'd2:out<=data2;
17              3'd3:out<=data3;
18              3'd4:out<=data4;
19              3'd5:out<=data5;   
20             default:out<=4'd0;
21         endcase
22 
23     end
24 
25 endmodule

 再写：

我只能说，当时真的喜欢用非阻塞……

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'b000:out=data0;
            3'b001:out=data1;
            3'b010:out=data2;
            3'b011:out=data3;
            3'b100:out=data4;
            3'b101:out=data5;
            default:out=3'b0;
        endcase
    end

endmodule

　　

posted @ 2023-04-20 00:15  江左子固  阅读(13)  评论(0)    收藏  举报