if statement latches

When designing circuits, you must think first in terms of circuits:

I want this logic gate
I want a combinational blob of logic that has these inputs and produces these outputs
I want a combinational blob of logic followed by a set of flip-flops
What you must not do is write the code first, then hope it generates a proper circuit.

If (cpu_overheated) then shut_off_computer = 1;
If (~arrived) then keep_driving = ~gas_tank_empty;

Always if2 - HDLBits (01xz.net)

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else 
            shut_off_computer=1'b0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
            keep_driving=1'b0;   //没有懂这个原理，还要再看
    end

endmodule

 再写：

根据这道题再复习一下latch锁存器、register寄存器、flipflop触发器

二、8【FPGA】Verilog中锁存器（Latch）原理、危害及避免_verilog latch-CSDN博客

当你在FPGA开发时想组合出纯组合逻辑电路（没有时钟控制端），但有时候你的代码最后综合出的结果却是“组合逻辑电路+锁存器（触发器）”。这说明在你的Verilog代码中有保持不变的情况，这种“保持输出不变”的行为意味着需要记住当前的状态，由于组合逻辑中的门电路是无法储存状态的，此时代码综合后就会产生锁存器（Latch)，来储存产生的状态。这就是组合逻辑中产生Latch的主要原因。
在组合逻辑电路的always中，if-else语句中不能缺少else；case语句中条件不能够完全列举或缺少default；在if-else和case中均不能出现变量自己将值赋给自己。这三种情况综合后会产生latch