always blocks(combinational)

Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit. Procedures (of which always blocks are one example) provide an alternative syntax for describing circuits.

For synthesizing hardware, two types of always blocks are relevant:

Combinational: always @(*)
Clocked: always @(posedge clk)
Combinational always blocks are equivalent to assign statements, thus there is always a way to express a combinational circuit both ways. The choice between which to use is mainly an issue of which syntax is more convenient. The syntax for code inside a procedural block is different from code that is outside. Procedural blocks have a richer set of statements (e.g., if-then, case), cannot contain continuous assignments, but also introduces many new non-intuitive ways of making errors. *(*Procedural continuous assignments do exist, but are somewhat different from continuous assignments, and are not synthesizable.)

For example, the assign and combinational always block describe the same circuit. Both create the same blob of combinational logic. Both will recompute the output whenever any of the inputs (right side) changes value. 
assign out1 = a & b | c ^ d;
always @(*) out2 = a & b | c ^ d;

Alwaysblock1 - HDLBits (01xz.net)

// synthesis verilog_input_version verilog_2001
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
assign out_assign=a&b;   //这种语法是康华光P71的数据流描述方法
    always@(*)
        out_alwaysblock<=a&b;
/*首先这个属于康华光P72的行为描述方法，其标识是always，always是一个循环执行语句，
在他后面跟着的执行循环中，只要括号内有任意一个量发生改变，则该语句就会被再执行一次
再其次这道题等于是定义了两种变量，一种是线网类型，用wire；另一种是寄存器类型，见康华光P63，P72
但是还是没看懂这里<=的意思*/
endmodule

 再写：

out_alwaysblock=a&b; 这样的写法也是可以的，虽然编译不报错，但是时序和组合还是分开的好