modules and vectors

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on : The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, selects how many cycles to delay the input, from zero to three clock cycles.) my_dff8sel[1:0]sel

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an block with a statement inside. (See also: alwayscasemux9to1v)

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q1,q2,q3;   //与上一题一样，这三个wire是要自己定义的，而对于clk、d则不需要
    //而且考虑到此题要求，定义一个八位的，故为[7:0]
    my_dff8 my_dff1(   //my_dff8这个类似于自己专属的模块名，然后在专属的模块名下再定义自己的第一、二、三个dff
        .clk(clk),   //clk这个形参在这里就定义为此处的实参clk
        .d(d),
        .q(q1)
    );
    my_dff8 my_dff2(
        .clk(clk),
        .d(q1),
        .q(q2)
    );
    my_dff8 my_dff3(
        .clk(clk),
        .d(q2),
        .q(q3)
    );
    always @(*) begin   /*首先是这个语法的使用，见康华光P209，当然
    此题还使用了LUT数据选择器的运用，见康华光P183，就能理解了以下的程序的含义*/
        case(sel)
            2'd0:q=d;
            2'd1:q=q1;
            2'd2:q=q2;
            2'd3:q=q3;
        endcase
    end

endmodule

 Module shift8 - HDLBits (01xz.net)

比较关键的就是要会、敢于定义中间量，其他的倒还好