Power-Aware GateSim Debug

For PAG debug, the following steps may be useful. 1. Get correct netlists from PD which contain power pins. 2. Fix ale file (src/meta/assembly/usb_t.ale.erb) to include netlists. 3. Ask for library from PD team and add the library into ale file (import/fch_misc/src/meta/assembly/fchtech_navi21.ale). (use *_pwr.v version library) 4. Make sure the timescale and fast mode ($STEM/import/snps_usb31_phy_tsmcN7/src/rtl/phy/include/dwc_usbc31dptxphy_phy_x4_ns_force_freq_tune.v) of phy netlist have been implemented. 5. to remain consistency with NLP simulation, ensure VDDCR_SOC_S5 and VDDCR_BACO could be set to correct values. That is, during coldboot we should supply on S5 power firstly then supply on S0 power, during S3 we should supply off S0 power firstly then supply on S0 power after wake up. 6. Fix compile issues. a. if there is library mismatch. b. if bind interfaces don't exist. c. if some signals have been Optimized away. 7. Fix run simulation issue. a. For bind interface issues in module_ovc_cfg, because of gate sim defines, maybe interfaces are not set correctly. b. Make sure VDD/VSS are connected(forced) corresponding value. c. Sometimes, VBN in PD netlist is not connected to VSS. need use lvs.v.gz instead of EcoRoute...v.gz. d. Some uninitialized DFF outputs need to $deposit only if S0 power is off, #1ns delay may be also needed for initial forever begin ...end block. e. AXI slave UVC reset should not reset during S3.

posted on 2019-09-03 14:32  jyaray  阅读(336)  评论(0编辑  收藏  举报