摘要: # APB TIMER 源码分析 ```verilog // Programmer's model // 0x00 RW CTRL[3:0] // [3] Timer Interrupt Enable // [2] Select External input as Clock // [1] Sele 阅读全文
posted @ 2023-08-21 19:41 FlowerDance、 阅读(231) 评论(0) 推荐(0)