Verilog Code Highlighter Example

基米 标签: Verilog,codehighlighter

Verilog Code Example

module DW01_add (A,B,CI,SUM,CO);

  parameter width=4;

  // port decalrations

  output [width-1 : 0]   SUM;
  output                 CO;
  input  [width-1 : 0]   A,B;
  input                  CI;

  reg    [width-1 : 0]   SUM;
  reg    [width-1 : 0]   sum_out;
  reg                    CO;
  reg                    c_out;

always 
  begin
    plus(sum_out,c_out,A,B,CI);
    SUM = sum_out;
    CO =  c_out;
  @(A or B or CI);
  end // process

  task plus;  
     output  [width-1 : 0] sumout;
     output                CO;
     input   [width-1 : 0] A,B;
     input                 CI;
     reg     [width-1 : 0] sumout,SUM;
     reg                      CO; 
     reg                      carry; 
     reg     [width-1 : 0] A,B;
     integer               i;

     begin
       carry = CI;
       for (i = 0; i <= width-1; i = i + 1) begin 
          sumout[i] = A[i] ^ B[i] ^ carry;
          carry = (A[i] & B[i]) | (A[i] & carry) | (carry & B[i]);
       end // loop
       SUM = sumout;
       CO = carry;
     end
  endtask // task 

  endmodule  // DW01_add;