练习一 数据比较器

ISE14.7，联合Modelsim SE仿真

模块源代码

`timescale 1ns / 1ps

module compare_test(
							equal,
							a,
							b
    );
	 input a,b;
	 output equal;
	 assign equal = (a==b)? 1:0;
	 //当a等于b时equal输出为1，不等输出0
endmodule

测试模块代码

`timescale 1ns / 1ns
module vtf_compare_test;
	// Inputs
	reg a;
	reg b;

	// Outputs
	wire equal;

	// Instantiate the Unit Under Test (UUT)
	compare_test uut (
		.equal(equal), 
		.a(a), 
		.b(b)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
		#100 a = 0;b = 1;
		#100 a = 1;b = 1;
		#100 a = 1;b = 0;
		#100 a = 0;b = 0;
		
		#100	$stop;
        
	

	end     
endmodule

仿真波形