练习二 二分频

ISE14.7，联合Modelsim SE仿真

模块源代码

`timescale 1ns / 1ps

module half_clk_test(
							reset,
							clk_in,
							clk_out
    );
	input clk_in,reset;
	output clk_out;
	reg clk_out;
	always @(posedge clk_in)
		begin
			if(!reset)	clk_out = 0;
			else 			clk_out = ~clk_out;
		end

endmodule

测试模块代码

`timescale 1ns / 100ps
`define clk_cycle 50

module vtf_half_clk_test;

	// Inputs
	reg reset;
	reg clk_in;

	// Outputs
	wire clk_out;

	// Instantiate the Unit Under Test (UUT)
	half_clk_test uut (
		.reset(reset), 
		.clk_in(clk_in), 
		.clk_out(clk_out)
	);

//产生测试时钟
	always  #`clk_cycle		clk_in = ~clk_in;
	//注意这边引用宏定义时的写法
	initial begin
		// Initialize Inputs
		reset = 1;
		clk_in = 0;
		#10	reset = 0;
		#110	reset = 1; 
		// Wait 100 ns for global reset to finish
		#100000	$stop;
        
		// Add stimulus here

	end
      
endmodule

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