练习五 always块实现较复杂的组合逻辑电路

模块源代码

`timescale 1ns / 1ps
`define plus	3'd0
`define minus	3'd1
`define band	3'd2
`define bor		3'd3
`define unegate	3'd4
//
// Company: 
// Engineer: 
// 
// Create Date:    15:41:41 07/26/2019 
// Design Name: 
// Module Name:    alu_test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module alu_test(
					out,
					opcode,
					a,
					b
    );
	output [7:0]out;
	reg [7:0]out;
	input [2:0]opcode;
	input [7:0]a,b;	//操作数
	always @(opcode or a or b)		//电平敏感的always块
		begin
			case(opcode)
				`plus:	out = a+b;	//加
				`minus:	out = a-b;	//减
				`band:	out = a&b;	//求与
				`bor:		out = a|b;	//求或
				`unegate:	out = ~a;	//求反
				default:		out = 8'hx;	//	未收到指令，输出任意态
			endcase
		end

endmodule

测试代码

`timescale 1ns / 1ns


// Company: 
// Engineer:
//
// Create Date:   15:56:26 07/26/2019
// Design Name:   alu_test
// Module Name:   D:/FPGA/project/alu_test/testbench/vtf_alu_test.v
// Project Name:  alu_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: alu_test
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module vtf_alu_test;

	// Inputs
	reg [2:0] opcode;
	reg [7:0] a;
	reg [7:0] b;

	// Outputs
	wire [7:0] out;

	parameter	times = 5;
	
	// Instantiate the Unit Under Test (UUT)
	alu_test uut (
		.out(out), 
		.opcode(opcode), 
		.a(a), 
		.b(b)
	);

	initial begin
		a = {$random}%256;
		b = {$random}%256;
		opcode = 3'h0;
		repeat(times)
			begin
				#100	a = {$random}%256;
						b = {$random}%256;
						opcode = opcode+1;
			end
			
		#100	$stop;
						
	end
      
endmodule

仿真波形