牛客进阶题目13：时钟分频（偶数）

用计数器来翻转即可

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg     clk_2       ;
reg     clk_4       ;
reg     clk_8       ;
reg     cyc_cnt_2   ;
reg[1:0]cyc_cnt_4   ;

always @(posedge clk_in or negedge rst) begin
    if(!rst)
        cyc_cnt_2 <= 1'b0 ;
    else
        cyc_cnt_2 <= cyc_cnt_2 + 1 ;
end

always @(posedge clk_in or negedge rst) begin
    if(!rst)
        cyc_cnt_4 <= 2'b0 ;
    else
        cyc_cnt_4 <= cyc_cnt_4 + 1 ;
end

always @(posedge clk_in or negedge rst) begin
    if(!rst)
        clk_2 <= 1'b0 ;
    else
        clk_2 <= ~clk_2 ;
end

always @(posedge clk_in or negedge rst) begin
    if(!rst)
        clk_4 <= 1'b0 ;
    else if(!cyc_cnt_2)
        clk_4 <= !clk_4 ;
    else
        clk_4 <= clk_4 ;
end

always @(posedge clk_in or negedge rst) begin
    if(!rst)
        clk_8 <= 1'b0 ;
    else if(!(cyc_cnt_4[0]||cyc_cnt_4[1]))
        clk_8 <= ~clk_8 ;
    else
        clk_8 <= clk_8 ;
end

assign clk_out2 = clk_2 ;
assign clk_out4 = clk_4 ;
assign clk_out8 = clk_8 ;
//*************code***********//
endmodule