牛客进阶题目6：数据串并转换电路

接收6个bit之后下一拍输出一个6bit宽的data，注意此时如果valid_a拉高，也要接收新进来的数据

这里用移位寄存器计数不太行，不太好让data_b在新数据出来前保持不变，虽然功能一样，但提交不通过

因此只能采用计数器来来方便进行条件判断

`timescale 1ns/1ns
module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg 	[5:0]		seq_shift;
reg 	[2:0]		seq_cnt;

always @(posedge clk or negedge rst_n ) begin
	if(!rst_n) 
		seq_cnt <= 'd0;
	else if(valid_a && ready_a)
		seq_cnt <= (seq_cnt == 3'd5) ? 'd0 : (seq_cnt + 1'd1);
end
always @(posedge clk or negedge rst_n ) begin
	if(!rst_n) 
		seq_shift <= 'd0;
	else if(valid_a && ready_a)
		seq_shift <= {data_a, seq_shift[5:1]};
end

always @(posedge clk or negedge rst_n ) begin
	if(!rst_n)begin
		valid_b <= 'd0;
		data_b <= 'd0;
	end 
	else if(seq_cnt[2]&seq_cnt[0]&(~seq_cnt[1]))begin
		valid_b <= 1'd1;
		data_b <= {data_a, seq_shift[5:1]};
	end
	else
		valid_b <= 'd0;
end

always @(posedge clk or negedge rst_n ) begin
	if(!rst_n) 
		ready_a <= 'd0;
	else 
		ready_a <= 1'd1;
end
endmodule

移位寄存器思路贴在下边，此时data_b在新数据出来前输出为0，提交不通过

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	 		ready_a		,
 	output			valid_b		,
	output   [5:0] 	data_b
);

reg[6:0]	seq_temp	;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		seq_temp <= 7'b1_000_000 ;
	else if(seq_temp[0]&valid_a&ready_a)
		seq_temp <= {data_a,6'b1_000_00} ;
	else if(valid_a && ready_a)
		seq_temp <= {data_a,seq_temp[6:1]} ;
	else
		seq_temp <= seq_temp ;
end

assign data_b  = seq_temp[0] ? seq_temp[6:1] : 6'd0 ;
assign valid_b = seq_temp[0] ? 1'b1 : 1'b0 	;
assign ready_a = 1'b1 ;

endmodule