Count clock

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

 

 

 

 

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss);

   
    always @(posedge clk)
        begin
            if( reset)
                begin
                ss <= 8'h00;
                end
            else if( ena)
            begin               
                if( ss == 8'h59)
                    begin
                        ss <= 8'h00;
                    end
                else if( ss[3:0] == 9)
                    begin
                        ss[3:0] <= 0;
                        ss[7:4] <= ss[7:4]+1;
                    end
                else
                    begin
                        ss[3:0] <= ss[3:0]+1;
                    end
            end
        end
   
    always @(posedge clk)
        begin
            if( reset)
                begin
                mm <= 8'h00;
                end
            else if( ena)
            begin               
                if(ss == 8'h59)
                begin
                if( mm == 8'h59)
                    begin
                        mm <= 8'h00;
                    end
                else if( mm[3:0] == 9)
                    begin
                        mm[3:0] <= 0;
                        mm[7:4] <= mm[7:4]+1;
                    end
                else
                    begin
                        mm[3:0] <= mm[3:0]+1;
                    end
                end 

            end
        end

 

    always @(posedge clk)
        begin
            if( reset)
                begin
                hh <= 8'd18;
                end
            else if( ena)
            begin   
                if(ss == 8'h59 && mm == 8'h59)
                begin
                if( hh == 8'h12)
                    begin
                        hh <= 1;
                    end
                else if( hh[3:0] == 9)
                    begin
                        hh[3:0] <= 0;
                        hh[7:4] <= hh[7:4]+1;
                    end
                else
                    begin
                        hh[3:0] <= hh[3:0]+1;
                    end
                end
            end
        end
   
    always @(posedge clk)
        begin
            if( reset)
                begin
                pm <= 0;
                end
            else if( hh==8'h11&&mm==8'h59&&ss==8'h59)
                    pm <= ~pm;
        end
   
endmodule