流水灯#DE10-Lite#Verilog

流水灯

 

实验板：DE10-Lite

 

资源：1. 按键复位：

 

2. led

 

 

3. 时钟

 

 

引脚分配：

信号名	管脚名	管脚号
clk	MAX10_CLK1_50	P11
rst_n	KEY0	B8
led	LEDR9	B11
	LEDR8	A11
	LEDR7	D14
	LEDR6	E14
	LEDR5	C13
	LEDR4	D13
	LEDR3	B10
	LEDR2	A10
	LEDR1	A9
	LEDR0	A8

 代码：

module led_run(
input clk,rst_n,
output reg [ 3:0] led);

reg [24:0] cnt;
reg clk_1s;
parameter T = 2500_0000;

always @(posedge clk,negedge rst_n)
begin
if(!rst_n)
begin
clk_1s <= 0;
cnt <= 0;
end
else
if(cnt < T - 1)
cnt <= cnt + 1;
else
begin
cnt <= 0;
clk_1s <= ~clk_1s;
end
end

always @(posedge clk_1s,negedge rst_n)
begin
if(!rst_n)
led <= 4'b1000;
else
led <= {led[2:0],led[3]};
end

endmodule

测试代码：

`timescale 1ns/1ps
module led_run_tb;
reg clk,rst_n;
wire [ 3:0] led;

defparam dut.T = 25;

led_run dut(
.clk(clk),
.rst_n(rst_n),
.led(led));

initial begin
clk = 0;
rst_n = 0;
#200.1 rst_n = 1;
#5000 $stop;

end

always #10 clk = ~clk;

endmodule

仿真结果：