串行数据接收判断-HDLbits

要求判断一段串行数据是否接收成功，（done=1）.数据帧的起始位是0，中间八位数据，结束位是1.

从空闲状态开始，也就是初始状态是1，当接收到0，进入启动状态，然后每个数据位是1个状态，接收到1进入停止位，接收到0进入

错误状态，直到接收到1，返回初始状态。（这里往往会把错误状态忽略）

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter IDLE=0,START=1,DATA0=2,DATA1=3,DATA2=4,DATA3=5,DATA4=6,
DATA5=7,DATA6=8,DATA7=9,STOP=10,ERROR=11;
reg[3:0]state,next_state;

always @(*)
case(state)
IDLE:next_state=in?IDLE:START;
START:next_state=DATA0;
DATA0:next_state=DATA1;
DATA1:next_state=DATA2;
DATA2:next_state=DATA3;
DATA3:next_state=DATA4;
DATA4:next_state=DATA5;
DATA5:next_state=DATA6;
DATA6:next_state=DATA7;
DATA7:next_state=in?STOP:ERROR;
STOP:next_state=in?IDLE:START;
ERROR:next_state=in?IDLE:ERROR;
default:next_state=IDLE;
endcase

always @(posedge clk)
if(reset)
state<=IDLE;
else
state<=next_state;

assign done=state==STOP;
endmodule