用BCD计数器编写一个12小时制的时钟

hdlbits的练习题，难点在于12小时的时钟模式分成半夜12AM-01-11AM-中午12PM----11PM-半夜12PM循环，PM在不同范围取反，BCD进位使能。

module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
cnt60 s(clk,reset,ena,ens,ss);
cnt60 m(clk,reset,ens,enm,mm);
cnt12 h(clk,reset,enh,pm,hh);
wire enm,ens,enh;
assign enh=enm&&ens;
endmodule
module cnt12(
input clk,
input reset,
input en,
output reg pm,
output reg [7:0]q);
always @(posedge clk)
if(reset)
begin
q[7:4]<=4'd1;
q[3:0]<=4'd2;
pm<=1'b0;
end
else if(en)
begin
if(q[7:4]==4'd1&&q[3:0]==4'd1)//11
begin
q[7:4]<=4'd1;
q[3:0]<=4'd2;
pm<=~pm;
end
else if(q[7:4]==4'd1&&q[3:0]==4'd0)//10
begin
q[7:4]<=q[7:4];
q[3:0]<=q[3:0]+1'b1;

end
else if(q[7:4]==4'd0&&q[3:0]==4'd9)//09
begin
q[7:4]<=4'd1;
q[3:0]<=4'd0;

end
else if(q[7:4]==4'd0&&q[3:0]<4'd9)//<09
begin
q[7:4]<=q[7:4];
q[3:0]<=q[3:0]+1'b1;

end
else if(q[7:4]==4'd1&&q[3:0]==4'd2)//12
begin
q[7:4]<=4'd0;
q[3:0]<=4'd1;

end
end
else
begin
q[7:4]<=q[7:4];
q[3:0]<=q[3:0];
end
endmodule
module cnt60(
input clk,
input reset,
input en,
output co,
output reg [7:0]q);
always @(posedge clk)
if(reset)

q<=8'd0;
else if(en)
begin
if(q[7:4]==4'd5&&q[3:0]==4'd9)
q<=8'd0;
else if(q[3:0]==4'd9)
begin
q[3:0]<=4'd0;
q[7:4]<=q[7:4]+1'b1;
end
else
begin
q[3:0]<=q[3:0]+1'b1;
q[7:4]<=q[7:4];
end
end
else
q<=q;
assign co=(q[7:4]==4'd5)&&(q[3:0]==4'd9);
endmodule