在Quartus II下产生无源代码网表设计文件方法

http://blog.sina.com.cn/s/blog_6276d01c01010izc.html

 从安全角度考虑， 我们常希望保证我们设计的私有性。一个有效的方法就是利用QuartusII Exported Partition file(.qxp)创建用于综合或布局布线网表文件(不包括源代码。这种增量编译的特点需要一个完整QuartusII 许可的支持(比如免费的web 版本的许可不支持的)。
    把原始设计作为一个.qxp文件发送的过程在QuartusII 手册的Quartus II Incremental Compilation for Hierarchical & Team-Based Design 章 节"Using an Exported Partition to Send a Design without Including Source Files"部分被描述。
    为了输出你的完整的设计，或部分设计，或被别人重复使用的设计，可以创建一个design partition 输出它。然后需要者把这个partition 导入到一个新的project。为了使用this simple aspect of an incremental flow，你不必对项目创建别的design partition 或添加floorplan assignments.关于使用增量编译commands更详细的细节,请参考手册相关章节！
    为了输出一个设计模块并且发送给别人使用，需要完成下面的步骤：
    1.  提供器件系列名字给接收人(比如CYCLONE II EP2C35 ，EP2C20等等)。 如果你要发送带综合网表的布局布线信息，也需要提供准确的器件选择，以便接收者能正确设置他们的项目。
    2.  创建一个文件或一个简单例化来定义这个设计模块的端口接口 ，并且把这个文件或实例化提供给接收人，以便在顶层设计中作为一个空partition来实例化这个模块。
      特别说明: 在Quartus II 7.2 SP3 或更早的版本中， 必须发送一个空黑盒模块/实体 定义，该空黑盒模块/实体列出端口宽度和方向。 在Quartus II 8.0后不需要这样的文件。
    3.  输出the appropriate level of hierarchy 到一个.qxp文件。 如果在Project menu,使用Quartus II GUI，请choose Export Design Partition and select the Partition hierarchy to export。
    4.  如果不需要发送布局布线信息，请仅选择选项Post-synthesis netlist。 如果接收人需要重新生成你的准确的布局布线结果，你需要选择项Post-fit netlist，同时也可选Export routing 选项包括布局布线信息。
    5. 提供.qxp文件给接收人，记住你不需要发送你源代码给接收者！
 
    接收者收到这个.qxp文件， 需要集成这个设计模块到顶层设计中，需要完成下面的步骤：
    1.  需要创建一个Quartus II 顶层设计项目 并且确保该项目目标器件与该.qxp文件目标器件相同(或者说至少相同器件系列(在不包括布局布线信息前提下)。
    2.  使用提供的端口信息实例这个设计模块；将相应的.qxp文件添加到Project Navigator中。
    3.  在Porcessing Menu 上， 点击Start/Perform Analysis & Elaboration， 验证该设计的层次。
    4.  为这个设计模块实例创建一个design partition。 Right-click the instance name in the Project Navigator， and choose Set as design partition。
    5.  导入这个.qxp文件到相关的partition hierarchy。 如果你使用the Quartus II GUI， 则在Project menu，选择Import Design Partition，select the partition for the design block， and browse to the .qxp file provided。
    6.  如果发送者还提供布局布线信息，也能控制是否保存输入网表，布局或布局布线信息。On the Assignments menu， choose Design Partitions Window， and adjust the settings as required。现在，拥有一个包含原始设计网表的完整设计，但不包括源文件。 项目包括输入指定，其他综合信息都包括在.qxp文件中。在RTL中只能看到相应的模块例化，但是里面是空的；在Chip Planner中可以看到模块的一些节点。
 
附件:(原始英文)
(链接：http://www.altera.com/support/kdb/solutions/rd06242008_7.html)
How_can_I create a design netlist without including my source design files?
Description
If you want to keep your design files private for security reasons, one option is to use a Quartus® II Exported Partition file (.qxp) to create a post-synthesis or post-fitting netlist without including any source design files. These incremental compilation features require a full Quartus II subscription license (and are not included with the free web edition license). Refer to the Related Solutions below for another alternative and other relation information.
The procedure to send your design as a .qxp file is documented in the section "Using an Exported Partition to Send a Design without Including Source Files" in the Quartus II Incremental Compilation for Hierarchical & Team-Based Design chapter of the Quartus II Handbook, and is included here for convenience.
To export your complete design, or part of your design, to be re-used by someone else, you create a design partition, export it, and then the recipient imports the partition into a new project.  To use this simple aspect of an incremental flow, you do not have to create any other design partitions or add floorplan assignments to your project. For more details about using the incremental compilation commands, refer to the handbook chapter.
Perform the following steps to export a design block and send it to someone else:
1.Provide the device family name to the recipient. If you send placement information with the synthesized netlist, also provide the exact device selection so they can set up their project to match.
2.Create documentation or a sample instantiation that defines the port interface for the design block and provide it to the recipient so he or she can instantiate the block as an empty partition in the top-level design.
o  In Quartus II software versions 7.2 SP3 and earlier, you must send an empty black box module/entity definition that lists the port widths and directions for the design block. Such a file is not needed beginning with version 8.0.
3.Export the appropriate level of hierarchy into a single .qxp file. If you use the Quartus II GUI, on the Project menu, choose Export Design Partition and select the Partition hierarchy to export.
4.Select the option to include just the Post-synthesis netlist if you do not need to send placement information. If the recipient wants to reproduce your exact Fitter results, you can select the Post-fit netlist option, and optionally enable Export routing to include routing information as well.
5.Provide the .qxp file to the recipient. Note that you do not have to send any of your design source code.
As the recipient of a .qxp file, incorporate the design block into a top-level design by performing the following steps:
1.Create a Quartus II project for the top-level design and ensure that your project targets the same device (or at least the same device family if the .qxp file does not include placement information), as specified by the sender.
2.Instantiate the design block using the port information provided.
3.On the Processing menu, point to Start and click Perform Analysis & Elaboration to identify the design hierarchy.
4.Create a design partition for the design block instance. Right-click the instance name in the Project Navigator, and choose Set as design partition.
5.Import the .qxp file for the appropriate partition hierarchy. If you use the Quartus II GUI, on the Project menu, choose Import Design Partition, select the partition for the design block, and browse to the .qxp file provided.
6.If the sender provided fitter information, you can control whether to preserve the imported netlist only, placement, or placement and routing, with the Fitter Preservation Level. On the Assignments menu, choose Design Partitions Window, and adjust the settings as required.
You now have a complete design that uses the original design netlist but does not include the source design files.  The project includes imported assignments and any post-compilation information that was included in the .qxp file.