UPF Fundamentals Workshop

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UPF Lab

Learning Objectives

After completing this lab, you should be able to:

• Understand the different components of the power intent of a design
• Create a UPF file based on the power intent description
• Use DC and MVRC to Verify the correctness and completeness of the UPF with respect to the design and power state table

Core Overview

 

 

For out lab, we consider two levels of power domain hierarchy: top level, and pd_switchable. The logical hierarchy block pd_switchable can be shutdown and has a low operating voltage than the top level.

Core Power Intent

 

• Top level logic and P0 block are always on, operating at 1.08V
• Logic block pd_switchable (containing tbmem0, cmem0, and rf0) has a switchable supply, operating at 0.7V
• All domains share a common ground VSS, oprating at 0.0V
• No state retention used
• Power sequencing is controlled via external interface:
  • Pwron_pd_n – domain is shutdown when signal is low
  • Pwron_iso_n –outputs isolated when signal is low
  • When domain is isolated, outputs are clamped to 1

Operational States

The valid operating states for the Leon3s design are:

  --Run –everything powered up and running

  --Idle –pd_switchable shut down

Leon3s supply nets (with corresponding voltages and port state names):

  -- VDD is always on at 1.08V (HV)

  -- VDD_LOW is always on at 0.7V (LV)

  -- VDD_LOW_SW is the output of the power switch;

                     It is either operating at 0.7V (LV) or “off” (OFF)

  -- VSS is always on at 0.0V (GND)

 

 

The following slides from the lecture material are included here to assist you with the labs.

Power supply network –create ports

 

• Power domains

create_power_domain TOP

create_power_domain pd1 –element u-dhm_core

• Create top level supply support

create_supply_port VDD

create_supply_port VDDL

create_supply_port VSS

 

Power supply network – create nets

 

• Create supply nets at top level

create_supply_net VDD –domain TOP

create_supply_net VDDL –domain TOP

create_supply_net VSS –domain TOP

 

• Create supply nets at child level(NOTE: power switch is not yet defined, but shown here for clarity)

 

create_supply_net VDDL –domain pd1 –reuse

create_supply_net VSS –domain pd1 –resuse

create_supply_net VDDLS1 –domain pd1

Power supply network –connect net

 

• Connect supply nets to ports

connect_supply_net VDD –ports {VDD}

connect_supply_net VDDL –ports VDDL

connect_supply_net VSS –ports {VSS}

Power supply network – Domain nets

 

• Specify primary nets for power domains

set_domain_supply_net TOP –primary_power_net VDD –primary_ground_net VSS

set_domain_supply_net pd1 –primary_power_net VDDLS1 –primary_ground_net VSS

• These are now the default power and ground connections for standard cells in those power domains.
  • Will be associated to the std_cell_main_rail attribute of all cells in this domain.

 

 

Retention Register Example

 

set_retention pd1_ret –domain pd1 –retention_power_net VDDL –retention_ground_net VSS

set_retention_control pd1_ret –domain pd1 –save_signal {save high} –restore_signal {restore high}

map_retention_cell pd1_ret –domain pd1 –lib_cell_type RDFFSRX1