32位CPU与RAM Disk——作妖式创新:-)

也许可以：

4GB内存对于桌面办公和不少应用足够了。

32位CPU集成4GB HBM内存，内存带宽高。

16~64GB DRAM通过NVMe与系统相连，声称自己是SSD。把pagefile.sys或交换分区放在其上。同时运行多个耗内存的程序，性能也不会太差。

RAM Disk还可用来放临时文件，做完计算后再把数据copy出来。

把旧服务器上的ECC DDR3用上。

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In the early 2000s, a further innovation was introduced: double data rate (DDR), which allows a DRAM to transfer data both on the rising and the falling edge of the memory clock, thereby doubling the peak data rate.

The newest innovation in 2017 in DRAMs is a packaging innovation, rather than a circuit innovation. It places multiple DRAMs in a stacked or adjacent fashion embedded within the same package as the processor. (Embedded DRAM also is used to refer to designs that place DRAM on the processor chip.) Placing the DRAM and processor in the same package lowers access latency (by shortening the delay between the DRAMs and the processor) and potentially increases bandwidth by allowing more and faster connections between the processor and DRAM; thus several producers have called it high bandwidth memory (HBM).

One version of this technology places the DRAM die directly on the CPU die using solder bump technology to connect them. Assuming adequate heat management, multiple DRAM dies can be stacked in this fashion. Another approach stacks only DRAMs and abuts them with the CPU in a single package using a substrate (interposer) containing the connections. Prototypes of HBM that allow stacking of up to eight chips have been demonstrated. With special versions of SDRAMs, such a package could contain 8 GiB of memory and have data transfer rates of 1 TB/s.

DRAM, SDRAM, DDR

SRAMs typically use six transistors per bit to prevent the information from being disturbed when read. SRAM needs only minimal power to retain the charge in standby mode. 4GB就是24G个晶体管。The M1 Max has 10 CPU cores and either 24 or 32 GPU cores depending on the configuration you get. At 57 billion transistors. the M1 Max is the largest CPU Apple has ever made while the M1 Pro has 33.7 billion transistors. Both are made on the same 5-nanometer process as the existing M1.

要啥Cache啊，哼哼。:-)

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Cache有多个way，比如4个。1~2个由程序指定，如指令cache_load mem_addr 把64个Byte cache起来。

程序还可以保证某段内存地址只有一个线程访问，绕开write back/through, coherent问题。cache_flush才写回内存。

MIPS有控制cache的指令。程序控制的数据cache和CPU控制的指令/数据cache共存。