Intel's infamous FDIV

Intel's infamous FDIV (floating point division) bug in the Pentium processor forced the company to recall chips after they had shipped at a total cost of $475 million in 1984. Logic simulation is essential to test a system before it is built.

In January 1984, gold was worth $360.65 per troy ounce. In 2021, gold was worth $1,799 per troy ounce. 即合23.7亿美元。

Logic synthesis transforms HDL code into a netlist describing the hardware (e.g., the logic gates and the wires connecting them). The logic synthesizer might perform optimizations to reduce the amount of hardware required. The netlist may be a text file, or it may be drawn as a schematic to help visualize the circuit.

One of the most common mistakes for beginners is to think of HDL as a computer program rather than as a shorthand for describing digital hardware. Instead, think of your system in terms of blocks of combinational logic, registers, and finite state machines. Sketch these blocks on paper and show how they are connected before you start writing code.

HDLs have specific ways of describing various classes of logic; these ways are called idioms. word, idiom, fluent都用来描述和语言有关的概念。

Reduction operators imply a multiple-input gate acting on a single bus. 就是个这：

module and8(input logic [7:0] a, output logic y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0];
endmodule

python:

>>> help(functools.reduce)
Help on built-in function reduce in module _functools:
reduce(...)
reduce(function, sequence[, initial]) -> value
Apply a function of two arguments cumulatively to the items of a sequence,
from left to right, so as to reduce the sequence to a single value.
For example, reduce(lambda x, y: x+y, [1, 2, 3, 4, 5]) calculates
((((1+2)+3)+4)+5). If initial is present, it is placed before the items
of the sequence in the calculation, and serves as a default when the
sequence is empty.

A 4:1 multiplexer can select one of four inputs, using nested conditional operators (? :).

Internal variables are neither inputs nor outputs; rather, they are used only internal to the module. They are similar to local variables in programming languages.

HDL assignment statements (assign in SystemVerilog and <= in VHDL) take place concurrently.

module fulladder(input logic a, b, cin, output logic s, cout);
logic p, g;
assign p = a ^ b;
assign g = a & b;
assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule