EDA学习笔记

Synthesis: Verilog Gates - MIT OpenCourseWare

 

Icarus Verilog的使用 博客园  Icarus Verilog for Windows (bleyer.org)

Verilog 环境搭建 | 菜鸟教程  SPICE简史 - 回声小站 - 博客园

OpenCores: EDA Tools   The 20 Best Electronic Design Automation Tools (EDA Tools) for Linux

gEDA有Windows版，能画图。Icarus和gEDA有合作。还不知道如何把.v文件变成门电路的电路图。

vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features. [没试]

Free IDE for VHDL and Verilog - Electrical Engineering Stack Exchange

1. think about a design you want to implement, e.g. an adder
2. implement the design in VHDL/Verilog
3. implement a testbench in VHDL/Verilog
4. use the testbench for simulating your design (from step 2)
5. if this works and the simulation is successful, try to synthesize the design
6. do all the other stuff, like map, place and route
7. build a .bit file
8. use your JTAG to program your FPGA

Sigasi. Either stand-alone, or plug-in to Eclipse. The free version doesn't have code refactoring functions and similar, but rather reduces to a "VHDL IDE".

EDA Playground is a web browser-based IDE that offers a choice of simulators.

Online VERILOG Runner (jdoodle.com)  verilog compiler download | SourceForge.net  那个几百KB的verilogx.jar不能用，JRE白装了。