| length | 0x0030 (Hex) |
| checksum | 0x0000 (Hex) |
| boot_mode | 0x001E (Hex) |
| portNum | 0x0000 (Hex) |
| swPllCfg_msw | 0x4014 (Hex) |
| swPllCfg_lsw | 0x0102 (Hex) |
| options | 0x0000 (Hex) |
| addressWidth | 0x0020 (Hex) |
| linkRateMhz | 0x09C4 (Hex) |
| refClock10kHz | 0x2710 (Hex) |
| window0Size | 0x0020 (Hex) |
| window1Size | 0x0020 (Hex) |
| window2Size | 0x0020 (Hex) |
| window3Size | 0x0020 (Hex) |
| vendorId | 0x104C (Hex) |
| deviceId | 0xB005 (Hex) |
| classCodeRevId_Msw | 0x0480 (Hex) |
| classCodeRevId_Lsw | 0x0001 (Hex) |
| serdesCfgMsw | 0x0000 (Hex) |
| serdesCfgLsw | 0x01C9 (Hex) |
| serdesCfgLane0Msw | 0x0006 (Hex) |
| serdesCfgLane0Lsw | 0x2320 (Hex) |
| serdesCfgLane1Msw | 0x0002 (Hex) |
| serdesCfgLane1Lsw | 0x2320 (Hex) |
posted @
2012-11-17 19:23
FPGA/DSP
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