摘要:
module Counter(clk, _rst, data, addr, PA, PB); input clk; input _rst; output [9:0] data; input [2:0] addr; input PA; input PB; wire readcs;wire enccs1, enccs2;wire pafedge0, pbfedge0;reg [3:0] code0;... 阅读全文
posted @ 2010-05-12 13:52 Johnson Cao 阅读(322) 评论(0) 推荐(0)
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