CPLD 正交计数和单向数据总线

module Counter(clk, _rst, data, addr, PA, PB);
    input clk;
    input _rst;
    output [9:0] data;
    input [2:0] addr;
    input PA;
    input PB;

wire readcs;
wire enccs1, enccs2;
wire pafedge0, pbfedge0;
reg [3:0] code0;
reg [21:0] cnt0;
reg [19:0] cntdata;
reg [9:0] readdata;
reg [1:0] csr;

//bus data
assign data = (readcs) ? readdata : 10'hzz;

//readcs
assign enccs1 = csr[0];
assign enccs2 = csr[1];
assign readcs = enccs1 | enccs2;

//CS signal
//always @(posedge clk or negedge _rst)
always @(posedge clk)
begin
   case(addr)
    3'H0: csr <= 2'b01;
    3'H1: csr <= 2'b10;
    default: csr <= 2'b00;
   endcase
end

//read pulse cnt or input
//always @(posedge clk or negedge _rst)
always @(posedge clk)
begin
   if (enccs1)
    readdata[9:0] = cntdata[9:0];
   else if (enccs2)
    readdata[9:0] = cntdata[19:10];
   else
    readdata[9:0] = 10'hzzz;
end

//pulse-------------------------------------------------
//pulse 4x
assign pafedge0 = (code0 == 4'b1000) | (code0 == 4'b1110) | (code0 == 4'b0111) | (code0 == 4'b0001);//PA first
assign pbfedge0 = (code0 == 4'b0100) | (code0 == 4'b1101) | (code0 == 4'b1011) | (code0 == 4'b0010);//PB first

always @(posedge clk or negedge _rst)
begin
   if(!_rst)
    code0 <= 0;
   else
   begin
    code0[1:0] <= code0[3:2];
    code0[3:2] <= {PA,PB};
   end
end
always @(posedge clk or negedge _rst)
begin
   if(!_rst)
    cnt0 <= 0;
   else
   begin
    if(pafedge0)
     cnt0 <= cnt0 + 1;
    else if(pbfedge0)
     cnt0 <= cnt0 - 1;
   end
end

//not 4x
always @(posedge enccs1 or negedge _rst)
begin
   if(!_rst)
    cntdata <= 0;
   else
   begin
    cntdata[19:0] <= cnt0[21:2];
   end
end

endmodule