封装好的全局时钟和复位测试模块 

 1 //---------   gSignal.v-------------------------
 2 
 3 `timescale 1ns/1ns 
 4 
 5 module gSignal(
 6                 gCLK,
 7                 gRST_N
 8                 );
 9     output reg gCLK;
10     output reg gRST_N;
11     
12     parameter    CLK_PERIOD    =    20;
13     parameter    LO_LEVEL    =    0;
14     parameter    HI_LEVEL    =    1;
15     
16     initial    gCLK    =    0;
17     always 
18         #(CLK_PERIOD/2)    gCLK    =    ~gCLK;                
19 
20     
21     initial    gRST_N    =    1;    
22     task sys_rst_n;
23         input [31:0]rst_n_time;
24         begin
25             gRST_N    =    LO_LEVEL;
26             #(rst_n_time);
27             gRST_N    =    HI_LEVEL;
28         end
29     endtask
30     
31 endmodule
posted @ 2012-03-01 14:57  fishplj2000  阅读(303)  评论(0)    收藏  举报