CSE6010计算机硬件中的各种缩写

针对D Latch D触发器：

• D: data input
• WE: write enable
• C: state only changes on rising edge of clock
• Q: data stored in flip flop

RAM:

• D:data
• A:address
• DI:data input
• DO:data output
• SRAM：静态RAM
• DRAM：动态RAM
• FSM：finite state machines

ISA:

• ISA： instruction set architecture
• HLL: high level language

Slides18 page18相关缩写：

• R1 R2： register1 register2
• ADD：做加法时用到的machine instruction set
• BRz offset: branch offset:分支调用时用到的machine instruction set
• JSR offset: jump sub routine:子程序调用时用到的machine instruction set
• RET:函数返回时用到的machine instruction set
• DR: destination register
• CC: conditional code
• BR: base register
• LDR: load register
• PC: program counter

Slides 19 page10相关缩写：

• MAR：memory address register(16 bits)
• LMAR: assert to load MAR register
• MDR: memory data register(16 bits)
• LMDR: assert to load MDR register
• MRd: Memory Read assert to read memory
• MWr: Memory write assert to write memory
• R: ready asserted when memory operation completed
• mux:多路复用器

Slides 19 Control and Status Signals
Control Signals:

• MRd: read memory
• MWr: write memory
• LPC: load program counter
• LIR: Load IR(instruction register)
• LMAR:
• LMDR:L都是表示Load
• MPC：PM mux
• MMAR: MAR mux
• MRF: register file mux
• MALU: ALU mux
• ALUop: ALU operation
• LCC: load condition codes
• RRd1: read RF port 1
• RRd2: read RF port 2;
• RWr: write RF
  Status Signals:
• R: memory operation completed
• 由于register是从左往右依次变小编码的 因此是从15~0
• IR[15:12]: 前四位代表opcode. IR[8:6]代表register S1
• N/Z/P: N/Z/P bit of condition code

Slides20 parrallels

• GPU
• FPGA(上诉两种都属于hardware accelerators)
• MIMD: multiple instruction stream, multiple data stream parallel computing
• SIMD: single instruction stream, multiple data stream computing.
• openMP:?
• MPI: Message passing interface

slides22:

• DMA: direct memory access
• Int: interrupt status signal