100 ms, 20 ms, PCIe PERST#, power-up, that somthing maybe confused you

The Two Critical Timing Windows

Timing	Specification	Description
20 ms	PCIe Base Spec §6.6	Endpoint must enter LTSSM Detect state after PERST# deassertion
100 ms	PCIe CEM Spec §3.1.3	Root Complex may begin enumeration/configuration cycles after PERST# deassertion

Power Valid
    │
    ├──[≥100ms]──► PERST# Deasserted (Fundamental Reset ends)
    │                  │
    │                  ├──[≤20ms]──► EP enters LTSSM Detect state ← Base Spec requirement
    │                  │
    │                  └──[≤100ms]──► RC may start config cycles ← CEM Spec requirement
    │
    ▼
System Boot Continues

PERST# Signal

Chap 2.2 - PCI Express Card Electromechanical Specification Revision 6.0, Draft 0.9
The PERST# signal is used to indicate when the power supply is within its specified voltage tolerance and is stable. It also initializes a component’s state machines and other logic once power supplies stabilize. On power-up, the de-assertion of PERST# is delayed 100 ms (TPVPERL) from the power rails achieving specified operating limits. Also, within this time, the reference clocks (REFCLK+, REFCLK-) also become stable, at least TPERST-CLK before PERST# is de-asserted. PERST# is asserted in advance of the power being switched off in a power-managed state like S3. PERST# is asserted when the power supply is powered down, but without the advanced warning of the transition.

For Endpoint or Switch

The first set of rules addresses requirements for components and devices:

• A component that supports Link speeds greater than 5.0 GT/s must enter the LTSSM Detect state within 100 ms of the end of Fundamental Reset (Link Training is described in § Section 4.2.5 ). A component that supports only Link speeds 5.0 GT/s or less must do this within 20 ms. All components are strongly encouraged to minimize this time period.