yangwang星空

inout口在modelsim仿真的方法 

//主要是// 和**********部分是关键
 1 `timescale 1ns/1ns
 2 module tb();
 3 
 4                   reg  main_clk;
 5                   reg [2:0] addr;
 6                   reg FPGA_CS0;//FPGA cs
 7                   reg RD;
 8                   reg WR;
 9                   wire arm_clk;
10                   wire led;
11               
12                   wire [15:0]data;        //*******
13                   reg [15:0] treg_data;  //关键部分
14                   integer i;            //
15                   
16                   
17 assign data = treg_data;               //*****  
18 
19 STM32_FPGA u1(
20                   .main_clk(main_clk),
21                   .arm_clk(arm_clk),
22                   .led(led),
23                   .addr(addr),
24                   .data(data),
25                   .FPGA_CS0(FPGA_CS0),//FPGAƬ
26                   .RD(RD),
27                   .WR(WR)
28                 
29                  );
30 
31 
32 initial begin
33     main_clk = 0;
34     addr = 3'd0;
35     FPGA_CS0 = 1;
36     RD = 1;
37     WR = 1;
38     i = 0;
39     treg_data = 0;
40     #200 
41     for(i=0;i<8;i=i+1)begin             //往FPGA寄存器写入8个随机数据
42         WR = 0 ;
43         addr = i;
44         treg_data = $random;
45         #20
46         WR = 1;
47         #20;
48     end
49     treg_data =16'bz;                 //写完后，treg_data 与 data 断开
50     #200    
51     for(i=0;i<8;i=i+1)begin           //从FPGA 寄存器读出8个数据
52         FPGA_CS0 = 0;    
53         RD = 0;    
54         addr = i;
55         #50;
56     end
57     FPGA_CS0 = 1;
58     RD = 1;
59     
60 
61     
62 end
63 
64 
65 always #20 main_clk = ~main_clk;
66 
67 
68 
69 endmodule

 

  1 /* 实际调试没有发现什么问题！ */

  2 module STM32_FPGA(
  3                       input  main_clk,
  4                       output arm_clk,
  5                       
  6                       output led,
  7                       
  8                       input [2:0] addr,
  9                       inout[15:0] data,
 10 
 11                     
 12                       input FPGA_CS0,//FPGA片选
 13                       input RD,
 14                       input WR
 15                      
 16                      );
 17 
 18 
 19 wire clk;
 20 
 21 pll_50M    pll_50M_inst (
 22                                 .inclk0 ( main_clk ),//25M
 23                                 .c0 ( clk ),         //50M
 24                                 .c1 ( arm_clk )      //8M                        
 25                              );
 26 
 27 
 28 reg [24:0] cnt = 0;
 29 always @(posedge clk)
 30   cnt <= cnt + 1'b1;             
 31 
 32 assign led = cnt[24];
 33 
 34 
 35 //AWE的上升沿，将数据写入FPGA寄存器
 36 
 37 
 38 reg [15:0] ARM_FPGA_REG0;                     
 39 reg [15:0] ARM_FPGA_REG1;
 40 reg [15:0] ARM_FPGA_REG2;                     
 41 reg [15:0] ARM_FPGA_REG3;                     
 42 reg [15:0] ARM_FPGA_REG4;
 43 reg [15:0] ARM_FPGA_REG5;                     
 44 reg [15:0] ARM_FPGA_REG6;                     
 45 reg [15:0] ARM_FPGA_REG7;                     
 46                      
 47 
 48 wire rd_en = ~FPGA_CS0 && ~RD;
 49 
 50 reg [15:0] data_reg;                     
 51 //always @(posedge clk) //DSP读操作,The sampling point of DSP reading is the risging edge of AWE!                               
 52 always @(*)
 53 begin                                                
 54    if(rd_en)                                 
 55      begin                                           
 56         case(addr[2:0])                              
 57          3'd0   :  data_reg <= ARM_FPGA_REG0;        
 58          3'd1   :  data_reg <= ARM_FPGA_REG1;        
 59          3'd2   :  data_reg <= ARM_FPGA_REG2;        
 60          3'd3   :  data_reg <= ARM_FPGA_REG3;        
 61          3'd4   :  data_reg <= ARM_FPGA_REG4;        
 62          3'd5   :  data_reg <= ARM_FPGA_REG5;        
 63          3'd6   :  data_reg <= ARM_FPGA_REG6;        
 64          3'd7   :  data_reg <= ARM_FPGA_REG7;        
 65          default:  data_reg<= 16'hzzzz;                                 
 66         endcase                                               
 67      end 
 68    else      data_reg<= 16'hzzzz; 
 69 end                                                           
 70 
 71 /* AWE下降沿DSP的数据写入FPGA，即sampling point */                     
 72                      
 73 reg WR_tmp1;
 74 reg WR_tmp2;
 75 always @(posedge clk)
 76 begin
 77     WR_tmp1 <= WR;
 78     WR_tmp2 <= WR_tmp1;
 79 end                     
 80                      
 81 wire WR_RISING = WR_tmp2 && ~WR_tmp1;//与clk同步         
 82 
 83                  
 84 always @(*)                                      
 85 begin                                              
 86   if(WR_RISING)                                
 87      begin                                    
 88         case(addr[2:0])                       
 89          3'd0   :  ARM_FPGA_REG0 <= data;     
 90          3'd1   :  ARM_FPGA_REG1 <= data;     
 91          3'd2   :  ARM_FPGA_REG2 <= data;     
 92          3'd3   :  ARM_FPGA_REG3 <= data;     
 93          3'd4   :  ARM_FPGA_REG4 <= data;     
 94          3'd5   :  ARM_FPGA_REG5 <= data;     
 95          3'd6   :  ARM_FPGA_REG6 <= data;     
 96          3'd7   :  ARM_FPGA_REG7 <= data;     
 97          default:  ;                          
 98         endcase                                        
 99      end 
100   else begin
101     ARM_FPGA_REG0 <= ARM_FPGA_REG0;
102     ARM_FPGA_REG1 <= ARM_FPGA_REG1; 
103     ARM_FPGA_REG2 <= ARM_FPGA_REG2;
104     ARM_FPGA_REG3 <= ARM_FPGA_REG3;
105     ARM_FPGA_REG4 <= ARM_FPGA_REG4;
106     ARM_FPGA_REG5 <= ARM_FPGA_REG5;
107     ARM_FPGA_REG6 <= ARM_FPGA_REG6;
108     ARM_FPGA_REG7 <= ARM_FPGA_REG7;
109   end     
110 end                                                
111  // assign data = rd_en ? data_reg : 16'hzzzz;
112 assign data = data_reg;  //可以用三目运算，但根据54行到68行逻辑判断，没有必要

113                  
114 endmodule

 参考原文http://blog.chinaaet.com/xzy610030/p/37525

 

posted on 2017-02-27 21:01  yangwang星空  阅读(933)  评论(0)    收藏  举报

导航