cordic算法的Verilog实现

cordic算法的Verilog实现

  1 module cordic
  2 
  3 #(parameter DATA_WIDTH=8)
  4 
  5 (
  6 
  7     input clk,
  8 
  9     input rst_n,
 10 
 11     input ena,
 12 
 13     input [DATA_WIDTH-1:0] phase_in,
 14 
 15     output reg [DATA_WIDTH-1:0] sin_out,
 16 
 17     output reg [DATA_WIDTH-1:0] cos_out,
 18 
 19     output reg [DATA_WIDTH-1:0] eps
 20 
 21 );
 22 
 23  
 24 
 25 localparam PIPELINE=8;
 26 
 27  
 28 
 29 reg [DATA_WIDTH-1:0] phase_in_reg;
 30 
 31 reg [DATA_WIDTH-1:0] x0,y0,z0;
 32 
 33 reg [DATA_WIDTH-1:0] x1,y1,z1;
 34 
 35 reg [DATA_WIDTH-1:0] x2,y2,z2;
 36 
 37 reg [DATA_WIDTH-1:0] x3,y3,z3;
 38 
 39 reg [DATA_WIDTH-1:0] x4,y4,z4;
 40 
 41 reg [DATA_WIDTH-1:0] x5,y5,z5;
 42 
 43 reg [DATA_WIDTH-1:0] x6,y6,z6;
 44 
 45 reg [DATA_WIDTH-1:0] x7,y7,z7;
 46 
 47  
 48 
 49 reg [1:0] quadrant [PIPELINE:0];
 50 
 51 integer i;
 52 
 53  
 54 
 55 always @(posedge clk,negedge rst_n)
 56 
 57 begin
 58 
 59     if(!rst_n)
 60 
 61         phase_in_reg <= 8'b0;
 62 
 63     else
 64 
 65         if(ena)
 66 
 67         begin
 68 
 69             case(phase_in[7:6])
 70 
 71                 2'b00: phase_in_reg <= phase_in;
 72 
 73                 2'b01: phase_in_reg <= phase_in-8'h40;
 74 
 75                 2'b10: phase_in_reg <= phase_in-8'h80;
 76 
 77                 2'b11: phase_in_reg <= phase_in-8'hc0;
 78 
 79                 default:;
 80 
 81             endcase
 82 
 83         end
 84 
 85 end
 86 
 87  
 88 
 89 always @ (posedge clk,negedge rst_n)
 90 
 91 begin
 92 
 93     if(!rst_n)
 94 
 95         begin
 96 
 97             x0<=8'b0;
 98 
 99             y0<=8'b0;
100 
101             z0<=8'b0;
102 
103         end
104 
105     else
106 
107         if(ena)
108 
109         begin
110 
111             x0 <= 8'h4D;       //0.60725*2^7
112 
113             y0 <= 8'h00;
114 
115             z0 <= phase_in_reg;
116 
117         end
118 
119 end
120 
121  
122 
123 //level 1
124 
125 always @ (posedge clk,negedge rst_n)
126 
127 begin
128 
129     if(!rst_n)
130 
131     begin
132 
133         x1 <=8'b0;
134 
135         y1 <=8'b0;
136 
137         z1 <=8'b0;
138 
139     end
140 
141     else
142 
143     if(ena)
144 
145         if(z0[7]==1'b0)
146 
147         begin
148 
149             x1 <= x0-y0;
150 
151             y1 <= y0+x0;
152 
153             z1 <=z0-8'h20;//45deg
154 
155         end
156 
157         else
158 
159         begin
160 
161             x1<=x0+y0;
162 
163             y1<=y0-x0;
164 
165             z1<=z0+8'h20;
166 
167         end
168 
169 end
170 
171 //level 2
172 
173 always @ (posedge clk,negedge rst_n)
174 
175 begin
176 
177     if(!rst_n)
178 
179     begin
180 
181         x2 <=8'b0;
182 
183         y2 <=8'b0;
184 
185         z2 <=8'b0;
186 
187     end
188 
189     else
190 
191     if(ena)
192 
193         if(z1[7]==1'b0)
194 
195         begin
196 
197             x2 <= x1-{y1[DATA_WIDTH-1],y1[DATA_WIDTH-1:1]};
198 
199             y2 <= y1+{x1[DATA_WIDTH-1],x1[DATA_WIDTH-1:1]};
200 
201             z2 <=z1-8'h12;//26deg
202 
203         end
204 
205         else
206 
207         begin
208 
209             x2<= x1+{y1[DATA_WIDTH-1],y1[DATA_WIDTH-1:1]};
210 
211             y2<= y1-{x1[DATA_WIDTH-1],x1[DATA_WIDTH-1:1]};
212 
213             z2<= z1+8'h12;
214 
215         end
216 
217 end
218 
219 //level 3
220 
221 always @ (posedge clk,negedge rst_n)
222 
223 begin
224 
225     if(!rst_n)
226 
227     begin
228 
229         x3 <=8'b0;
230 
231         y3 <=8'b0;
232 
233         z3 <=8'b0;
234 
235     end
236 
237     else
238 
239     if(ena)
240 
241         if(z2[7]==1'b0)
242 
243         begin
244 
245             x3 <= x2-{{2{y2[DATA_WIDTH-1]}},y2[DATA_WIDTH-1:2]};
246 
247             y3 <= y2+{{2{x2[DATA_WIDTH-1]}},x2[DATA_WIDTH-1:2]};
248 
249             z3 <=z2-8'h09;//14deg
250 
251         end
252 
253         else
254 
255         begin
256 
257             x3<= x2+{{2{y2[DATA_WIDTH-1]}},y2[DATA_WIDTH-1:2]};
258 
259             y3<= y2-{{2{x2[DATA_WIDTH-1]}},x2[DATA_WIDTH-1:2]};
260 
261             z3<= z2+8'h09;
262 
263         end
264 
265 end
266 
267 //level 4
268 
269 always @ (posedge clk,negedge rst_n)
270 
271 begin
272 
273     if(!rst_n)
274 
275     begin
276 
277         x4 <=8'b0;
278 
279         y4 <=8'b0;
280 
281         z4 <=8'b0;
282 
283     end
284 
285     else
286 
287     if(ena)
288 
289         if(z3[7]==1'b0)
290 
291         begin
292 
293             x4 <= x3-{{3{y3[DATA_WIDTH-1]}},y3[DATA_WIDTH-1:3]};
294 
295             y4 <= y3+{{3{x3[DATA_WIDTH-1]}},x3[DATA_WIDTH-1:3]};
296 
297             z4 <= z3-8'h04;//7deg
298 
299         end
300 
301         else
302 
303         begin
304 
305             x4<= x3+{{3{y3[DATA_WIDTH-1]}},y3[DATA_WIDTH-1:3]};
306 
307             y4<= y3-{{3{x3[DATA_WIDTH-1]}},x3[DATA_WIDTH-1:3]};
308 
309             z4<= z3+8'h04;
310 
311         end
312 
313 end
314 
315 //level 5
316 
317 always @ (posedge clk,negedge rst_n)
318 
319 begin
320 
321     if(!rst_n)
322 
323     begin
324 
325         x5 <=8'b0;
326 
327         y5 <=8'b0;
328 
329         z5 <=8'b0;
330 
331     end
332 
333     else
334 
335     if(ena)
336 
337         if(z4[7]==1'b0)
338 
339         begin
340 
341             x5 <= x4-{{4{y4[DATA_WIDTH-1]}},y4[DATA_WIDTH-1:4]};
342 
343             y5 <= y4+{{4{x4[DATA_WIDTH-1]}},x4[DATA_WIDTH-1:4]};
344 
345             z5 <= z4-8'h02;//4deg
346 
347         end
348 
349         else
350 
351         begin
352 
353             x5<= x4+{{4{y4[DATA_WIDTH-1]}},y4[DATA_WIDTH-1:4]};
354 
355             y5<= y4-{{4{x4[DATA_WIDTH-1]}},x4[DATA_WIDTH-1:4]};
356 
357             z5<= z4+8'h02;
358 
359         end
360 
361 end
362 
363 //level 6
364 
365 always @ (posedge clk,negedge rst_n)
366 
367 begin
368 
369     if(!rst_n)
370 
371     begin
372 
373         x6 <=8'b0;
374 
375         y6 <=8'b0;
376 
377         z6 <=8'b0;
378 
379     end
380 
381     else
382 
383     if(ena)
384 
385         if(z5[7]==1'b0)
386 
387         begin
388 
389             x6 <= x5-{{5{y5[DATA_WIDTH-1]}},y5[DATA_WIDTH-1:5]};
390 
391             y6 <= y5+{{5{x5[DATA_WIDTH-1]}},x5[DATA_WIDTH-1:5]};
392 
393             z6 <= z5-8'h01;//2deg
394 
395         end
396 
397         else
398 
399         begin
400 
401             x6<= x5+{{5{y5[DATA_WIDTH-1]}},y5[DATA_WIDTH-1:5]};
402 
403             y6<= y5-{{5{x5[DATA_WIDTH-1]}},x5[DATA_WIDTH-1:5]};
404 
405             z6<= z5+8'h01;
406 
407         end
408 
409 end
410 
411 //level 7
412 
413 always @ (posedge clk,negedge rst_n)
414 
415 begin
416 
417     if(!rst_n)
418 
419     begin
420 
421         x7 <=8'b0;
422 
423         y7 <=8'b0;
424 
425         z7 <=8'b0;
426 
427     end
428 
429     else
430 
431     if(ena)
432 
433         if(z6[7]==1'b0)
434 
435         begin
436 
437             x7 <= x6-{{6{y6[DATA_WIDTH-1]}},y6[DATA_WIDTH-1:6]};
438 
439             y7 <= y6+{{6{x6[DATA_WIDTH-1]}},x6[DATA_WIDTH-1:6]};
440 
441             z7 <= z6-8'h00;//2deg
442 
443         end
444 
445         else
446 
447         begin
448 
449             x7<= x6+{{6{y6[DATA_WIDTH-1]}},y6[DATA_WIDTH-1:6]};
450 
451             y7<= y6-{{6{x6[DATA_WIDTH-1]}},x6[DATA_WIDTH-1:6]};
452 
453             z7<= z6+8'h00;
454 
455         end
456 
457 end
458 
459 //-------
460 
461 always @ (posedge clk,negedge rst_n)
462 
463 begin
464 
465     if(!rst_n)
466 
467         for(i=0;i<=PIPELINE;i=i+1)
468 
469             quadrant[i]<=2'b00;
470 
471     else
472 
473         if(ena)
474 
475             begin
476 
477                 for(i=0;i<PIPELINE;i=i+1)
478 
479                     quadrant[i+1]<=quadrant[i];
480 
481                 quadrant[0]<=phase_in[7:6];
482 
483             end
484 
485 end
486 
487 //------------
488 
489 always @ (posedge clk,negedge rst_n)
490 
491 begin
492 
493     if(!rst_n)
494 
495     begin
496 
497         sin_out <= 8'b0;
498 
499         cos_out <= 8'b0;
500 
501         eps     <= 8'b0;
502 
503     end
504 
505     else
506 
507         if(ena)
508 
509         case(quadrant[7])
510 
511             2'b00:
512 
513                 begin
514 
515                     sin_out <= y6;
516 
517                     cos_out <= x6;
518 
519                     eps     <= z6;
520 
521                 end
522 
523             2'b01:
524 
525                 begin
526 
527                     sin_out <= x6;
528 
529                     cos_out <= ~(y6)+1'b1;
530 
531                     eps     <= z6;
532 
533                 end
534 
535             2'b10:
536 
537                 begin
538 
539                     sin_out <= ~(y6)+1'b1;
540 
541                     cos_out <= ~(x6)+1'b1;
542 
543                     eps     <= z6;
544 
545                 end
546 
547             2'b11:
548 
549                 begin
550 
551                     sin_out <= ~(x6)+1'b1;
552 
553                     cos_out <= y6;
554 
555                     eps     <= z6;
556 
557                 end
558 
559          endcase
560 
561 end
562 
563  
564 
565 endmodule
 

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posted on 2013-09-13 18:20  吴国华  阅读(502)  评论(0)    收藏  举报

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