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// Copyright 2018 ETH Zurich, University of Bologna and Greenwaves Technologies. // Copyright and related rights are licensed under the Solderpad Hard 阅读全文
posted @ 2021-04-13 09:36
digital-world
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摘要:
module rc_ram #(parameter RC_WIDTH = 22, parameter ADDR_WIDTH = 5, parameter INIT_FILE = "../testbench/rc.dat" ) ( input logic clk, input logic rst_n, 阅读全文
posted @ 2021-04-13 09:33
digital-world
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