摘要：
// Copyright 2018 ETH Zurich, University of Bologna and Greenwaves Technologies. // Copyright and related rights are licensed under the Solderpad Hard 阅读全文
摘要：
module rc_ram #(parameter RC_WIDTH = 22, parameter ADDR_WIDTH = 5, parameter INIT_FILE = "../testbench/rc.dat" ) ( input logic clk, input logic rst_n, 阅读全文