【随感杂想】RAM模型及时序

module rc_ram
#(parameter RC_WIDTH = 22, 
  parameter ADDR_WIDTH = 5,
  parameter INIT_FILE = "../testbench/rc.dat"
)
(
	input logic                  clk,
	input logic                  rst_n, 

	input logic                  en_i,
	input logic [ADDR_WIDTH-1:0] addr_i, 
	input logic                  we_i, 
	input logic [RC_WIDTH-1:0]  wdata_i,

	output logic [RC_WIDTH-1:0] rdata_o 

);

initial begin
	$readmemh(INIT_FILE, mem);
end

logic [RC_WIDTH-1:0] mem[2**ADDR_WIDTH];
logic [RC_WIDTH-1:0] data_retention;

always_ff @(posedge clk , negedge rst_n) begin
	if(~rst_n) begin
		data_retention <= 0;
	end 
	else begin
		if(en_i) begin
			data_retention <= mem[addr_i];
		end 
	end 
end 

assign rdata_o = en_i ? mem[addr_i] : data_retention;

always @(posedge clk) begin
	if (en_i & we_i) begin
		mem[addr_i] <= wdata_i;
	end 
end 
endmodule