时序逻辑设计之计数器

1. 设计定义

　　2. 设计输入

module led_flash(
    clk,
    rst,
    led 
        );
    input clk;
    input rst;
    output reg led;
    
    reg [24:0]cnt;
    always@(posedge clk or negedge rst)
        if(!rst)
            cnt <= 0;
        else if(cnt==25000000)
            cnt <= 0;
        else
            cnt <= cnt+1;
            
    always@(posedge clk or negedge rst)
        if(!rst)
            led <= 0;
        else if(cnt==25000000)
            led=!led;
endmodule

　　3. 功能仿真

`timescale 1ns / 1ns
module led_flash_tb;

    reg s_clk;
    reg s_rst;
    wire led;
    
   led_flash led_flash_tb(
    .clk(s_clk),
    .rst(s_rst),
    .led(s_led) 
        );

    initial   s_clk =1;
    always #10 s_clk=!s_clk;
        
    initial begin
        s_rst = 0;
        #201;
        s_rst = 1;
        #2000000000;
        $stop;
    end   
endmodule

 

 

　　4. 布局布线

　　5. 板级调试