组合逻辑电路设计之译码器

1. 设计定义

　　原理图

　　

　　2. 设计输入

　　

　　3. 分析综合

　　

　　4. 功能仿真

　　

`timescale 1ns / 1ns
module mux2_tb();
//例化 
 reg s_a;
 reg s_b;
 reg s_sel;
 wire out;
 mux2 mux2(
    .a(s_a),
    .b(s_b),
    .sel(s_sel),
    .out(s_out)
);

initial begin
    s_a = 0;s_b = 0; s_sel = 0;
    #200;
    s_a = 0;s_b = 0; s_sel = 1;
    #200;
    s_a = 0;s_b = 1; s_sel = 0;
    #200;
    s_a = 0;s_b = 1; s_sel = 1;
    #200;
    s_a = 1;s_b = 0; s_sel = 0;
    #200;
    s_a = 1;s_b = 0; s_sel = 1;
    #200;
    s_a = 1;s_b = 1; s_sel = 0;
    #200;
    s_a = 1;s_b = 1; s_sel = 1;
    #200;
end
endmodule

　　5. 时序仿真

输出有延迟和有毛刺

　　6. 板级调试