Static Timing Analysis(STA)一
A method for detemining if a circuit meets timing constraints without having to simulate clock cycles.
这句话说出了静态时序的真谛,区别于动态的,这是without!!
个人感觉STA中最重要的还是Timing path。识别一个design中有几个timing path,请看。。。
Timing path has a startpoint and an endpoint.
startpoints:
*Input ports(you should konw the difference between port and pin)
*clock pins of sequential devices
Endpoints:
*Output ports
*Data input pins of sequential devices
How many timing paths in the 1-36
As the rules said,we can find four timing paths:
A--->D1,A--->D2,clk--->D2,clk--->z(图片中左边的D更正为D1,右边的更正为D2)
可能有些人会想那A---Z算不算timing path???其实这个并不算,因为我们的timing path 是要在一个时钟周期内能够完成的,显然图片中A--->Z需要两个时钟周期的。
今天先介绍到这吧,待续。。。。
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