检测串行序列10010

module check10010(
input clk,din,rstn,
output reg dout);

reg [2:0] state;
reg [2:0] nextstate;

parameter state0 = 3'b000,
state1 = 3'b001,
state2 = 3'b010,
state3 = 3'b011,
state4 = 3'b100,
state5 = 3'b101;

always@ (posedge clk)
if (!rstn)
state <= state0;
else
state <= nextstate;


always@ (state or din) begin
case (state)
state0: if(din) nextstate = state1;
else nextstate = state0;

state1: if(din) nextstate = state1;
else nextstate = state2;

state2: if(din) nextstate = state1;
else nextstate = state3;

state3: if(din) nextstate = state4;
else nextstate = state0;

state4: if(din) nextstate = state1;
else nextstate = state5;

state5: if(din) nextstate = state1;
else nextstate = state3;

default: nextstate = state0;
endcase
end

always@ (*)
if (rstn==1 && state == state4 && (!din))
dout = 1;
else
dout = 0;

endmodule

 

 

 

 

quartus prime波形仿真：

 

内部结构图：

状态机state图：