myCPUZ （未完待续）

目前能获得一些功能鸟~~比如CPU厂商啊，支持的指令集啊，还有一些步进啊，型号啊什么的

CPU缓存信息我用的枚举，有别的好办法没啊。。。。累死了。

//cpuid.h
#define NOMORE_CACHE 	0
#define DATA_CACHE		1
#define	INS_CACHE			2
#define UNIFIED_CACHE		3

#define	__w						printf

const char *cache_type[] = {
			"No More Cache",
			"Data Cache",
			"Instruction Cache",
			"Unified Cache"
			};

const char *feature_flag_names[] = {
			"SSE3 ",	"PCLMULDQ ",	"DTES64 ",	"MONITOR ",	"DS-CPL ",	"VMX ",		"SMX ",		"SET ",
			"TM2 ",		"SSSE3 ",			"CNXT-ID ",	"- ",				"- ",			"CX16 ",	"xTPR ",	"PDCM ",
			"- ",			"- ",					"DCA ",			"SSE4.1 ",		"SSE4.2 ",	"x2APIC",	"MOVBE ",	"POPCNT ",
			"- ",			"AES ",				"XSAVE ",		"OSXSAVE ",	"- ",			" -",			"- ",			"- ",
			"FPU ",		"VME ",		"DE ",		"PSE",		"TSC ",		"MSR ",		"PEA ",		"MCE ",
			"CX8 ",		"APIC ",		"- ",			"SEP ",		"MTRR ",	"PGE ",		"MAC ",		"CMOV ",
			"PAT",		"PSE-36 ",	"PSN ",		"CLFSH ",	"- ",			"DS ",		"ACPI ",		"MMX ",
			"FXSR ",	"SSE ",		"SSE2 ",	"SS ",		"HTT ",		"TM ",		"- ",			"PBE "
			};

const char *descriptor_decode_values[] ={
			"", //0x00
			"Instruction TLB:4-KB Pages,4-way setassociative,32entries", //0x01
			"Instruction TLB:4-MB Pages,fully associative,2 entries", //0x02
			"Data TLB:4-KB Pages,4-way set associative,64 entries", // 0x03
			"Data TLB:4-MB Pages,4-way set associative,8 entries",// 0x04
			"Data TLB:4-MB Pages,4-way set associative,32 entries",//0x05
			"1st-level instruction cache:8-KB,4-way set associative,32-byte line size", //0x06
			"", //0x07
			"1st-level instruction cache:16-KB,4-way set associative,32-byte line size", //0x08
			"1st-level instruction cache:32-KB,4-way set associative,64-byte line size", //0x09
			"1st-level data cache:8-KB,2-way set associative,32-byte line size", //0x0a
			"", //0x0b
			"1st-level data cache:16-KB,4-way set associative,32-byte line size", //0x0c
			"1st-level data cache:16-KB,4-way set associative,64-byte line size", //0x0d
			"", //0x0e
			"", //0x0f
			"", //0x10
			"", //0x11
			"", //0x12
			"", //0x13
			"", //0x14
			"", //0x15
			"", //0x16
			"", //0x17
			"", //0x18
			"", //0x19
			"", //0x1a
			"", //0x1b
			"", //0x1c
			"", //0x1d
			"", //0x1e
			"", //0x1f
			"", //0X20
			"256-KB L2(MLC), 8-way set associative, 64-byte line size", //0x21
			"3rd-level cache 512-KB, 4-way set associative, sectored cache, 64-byte line size", //0x22
			"3rd-level cache 1-MB, 8-way set associative, sectored cache, 64-byte line size", //0x23
			"", //0x24
			"3rd-level cache 2-MB, 8-way set associative, sectored cache, 64-byte line size", //0x25
			"", //0x26
			"", //0x27
			"", //0x28
			"3rd-level cache 4-MB, 8-way set associative, sectored cache, 64-byte line size", //0x29
			"", //0x2a
			"", //0x2b
			"1st-level data cache: 32-KB,8-way set associative, 64-byte line size", //0x2c
			"", //0x2d
			"", //0x2e
			"", //0x2f
			"1st-level instruction cache: 32-KB,8-way set associative, 64-byte line size", //0x30
			"", //0x31
			"", //0x32
			"", //0x33
			"", //0x34
			"", //0x35
			"", //0x36
			"", //0x37
			"", //0x38
			"2nd-level level cache: 128-KB,4-way set associative, sectored cache, 64-byte line size", //0x39
			"2nd-level level cache: 192-KB,6-way set associative, sectored cache, 64-byte line size", //0x3a
			"2nd-level level cache: 128-KB,2-way set associative, sectored cache, 64-byte line size", //0x3b
			"2nd-level level cache: 256-KB,4-way set associative, sectored cache, 64-byte line size", //0x3c
			"2nd-level level cache: 384-KB,6-way set associative, sectored cache, 64-byte line size", //0x3d
			"2nd-level level cache: 512-KB,4-way set associative, sectored cache, 64-byte line size", //0x3e
			"", //0x3f
			"No 2dn-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache", //0x40
			"2nd-level cache: 128KB, 4-way set associative, 32-byte line size", //0x41
			"2nd-level cache: 256KB, 4-way set associative, 32-byte line size", //0x42
			"2nd-level cache: 512KB, 4-way set associative, 32-byte line size", //0x43
			"2nd-level cache: 1-MB, 4-way set associative, 32-byte line size", //0x44
			"2nd-level cache: 2-MB, 4-way set associative, 32-byte line size", //0x45
			"2nd-level cache: 4-MB, 4-way set associative, 64-byte line size", //0x46
			"2nd-level cache: 8-MB, 8-way set associative, 64-byte line size", //0x47
			"2nd-level cache: 3-MB, 12-way set associative, 64-byte line size", //0x48
			"2nd-level cache: 4-MB, 16-way set associative, 64-byte line size", //0x49
			"2nd-level cache: 6-MB, 12-way set associative, 64-byte line size", //0x4a
			"2nd-level cache: 8-MB, 16-way set associative, 64-byte line size", //0x4b
			"2nd-level cache: 12-MB, 12-way set associative, 64-byte line size", //0x4c
			"2nd-level cache: 16-MB, 16-way set associative, 64-byte line size", //0x4d
			"2nd-level cache: 6-MB, 24-way set associative, 64-byte line size", //0x4e
			"", //0x4f
			"Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries", //0x50
			"Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries", //0x51
			"Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries", //0x52
			"", //0x53
			"", //0x54
			"Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries", //0x55
			"L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries", //0x56
			"L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries", //0x57
			"", //0x58
			"", //0x59
			"Data TLB0:2-MB or 4-MB pages, 4-way associative, 32 entries", //0x5a
			"Data TLB0:4-KB or 4-MB pages, 4-way associative, 64 entries", //0x5b
			"Data TLB0:4-KB or 4-MB pages, 4-way associative, 128 entries", //0x5c
			"Data TLB0:4-KB or 4-MB pages, 4-way associative, 256 entries", //0x5d
			"", //0x5e
			"", //0x5f
			"1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size", //0x60
			"", //0x61
			"", //0x62
			"", //0x63
			"", //0x64
			"", //0x65
			"1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size", //0x66
			"1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size", //0x67
			"1st-level data cache: 32-KB, 4-way set associative, sectored cache, 64-byte line size", //0x68
			"", //0x69
			"", //0x6a
			"", //0x6b
			"", //0x6c
			"", //0x6d
			"", //0x6e
			"", //0x6f
			"Trace cache: 12K-uops, 8-way set associative", //0x70
			"Trace cache: 16K-uops, 8-way set associative", //0x71
			"Trace cache: 32K-uops, 8-way set associative", //0x72
			"Trace cache: 64K-uops, 8-way set associative", //0x73
			"", //0x74
			"", //0x75
			"", //0x76
			"", //0x77
			"2nd-level cache: 1-MB, 4-way set associative, 64-byte line size", //0x78
			"2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size", //0x79
			"2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size", //0x7a
			"2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size", //0x7b
			"2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size", //0x7c
			"2nd-level cache: 2-MB, 8-way set associative, 64-byte line size", //0x7d
			"", //0x7e
			"2nd-level cache: 512-KB, 2-way set associative, 64-byte line size", //0x7f
			"", //0x80
			"", //0x81
			"2nd-level cache: 256-KB, 8-way set associative, 32-byte line size", //0x82
			"2nd-level cache: 512-KB, 8-way set associative, 32-byte line size", //0x83
			"2nd-level cache: 1-MB, 8-way set associative, 32-byte line size", //0x84
			"2nd-level cache: 2-MB, 8-way set associative, 32-byte line size", //0x85
			"2nd-level cache: 512-KB, 4-way set associative, 64-byte line size", //0x86
			"2nd-level cache: 1-MB, 8-way set associative, 64-byte line size", //0x87
			"", //0x88
			"", //0x89
			"", //0x8a
			"", //0x8b
			"", //0x8c
			"", //0x8d
			"", //0x8e
			"", //0x8f
			"", //0x90
			"", //0x91
			"", //0x92
			"", //0x93
			"", //0x94
			"", //0x95
			"", //0x96
			"", //0x97
			"", //0x98
			"", //0x99
			"", //0x9a
			"", //0x9b
			"", //0x9c
			"", //0x9d
			"", //0x9e
			"", //0x9f
			"", //0xa0
			"", //0xa1
			"", //0xa2
			"", //0xa3
			"", //0xa4
			"", //0xa5
			"", //0xa6
			"", //0xa7
			"", //0xa8
			"", //0xa9
			"", //0xaa
			"", //0xab
			"", //0xac
			"", //0xad
			"", //0xae
			"", //0xaf
			"Instruction TLB:4-KB Pages, 4-way set associative, 128 entries", //0xb0
			"Instruction TLB:2-MB Pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries", //0xb1
			"Instruction TLB:4-KB Pages, 4-way set associative, 64 entries", //0xb2
			"Data TLB: 4-KB Pages, 4-way set associative, 128 entries", //0xb3
			"Data TLB: 4-KB Pages, 4-way set associative, 256 entries", //0xb4
			"", //0xb5
			"", //0xb6
			"", //0xb7
			"", //0xb8
			"", //0xb9
			"", //0xba
			"", //0xbb
			"", //0xbc
			"", //0xbd
			"", //0xbe
			"", //0xbf
			"", //0xc0
			"", //0xc1
			"", //0xc2
			"", //0xc3
			"", //0xc4
			"", //0xc5
			"", //0xc6
			"", //0xc7
			"", //0xc8
			"", //0xc9
			"Shared 2nd-level TLB: 4KB pages, 4-way seet associative, 512 entries", //0xca
			"", //0xcb
			"", //0xcc
			"", //0xcd
			"", //0xce
			"", //0xcf
			"512KB L3 Cache, 4-way set associative, 64-byte line size", //0xd0
			"1-MB L3 Cache, 4-way set associative, 64-byte line size", //0xd1
			"2-MB L3 Cache, 4-way set associative, 64-byte line size", //0xd2
			"", //0xd3
			"", //0xd4
			"", //0xd5
			"1-MB L3 Cache, 8-way set associative, 64-byte line size", //0xd6
			"2-MB L3 Cache, 8-way set associative, 64-byte line size", //0xd7
			"4-MB L3 Cache, 8-way set associative, 64-byte line size", //0xd8
			"", //0xd9
			"", //0xda
			"", //0xdb
			"1.5-MB L3 Cache, 12-way set associative, 64-byte line size", //0xdc
			"3-MB L3 Cache, 12-way set associative, 64-byte line size", //0xdd
			"6-MB L3 Cache, 12-way set associative, 64-byte line size", //0xde
			"", //0xdf
			"", //0xe0
			"", //0xe1
			"2-MB L3 Cache, 16-way set associative, 64-byte line size", //0xe2
			"4-MB L3 Cache, 16-way set associative, 64-byte line size", //0xe3
			"8-MB L3 Cache, 16-way set associative, 64-byte line size", //0xe4
			"", //0xe5
			"", //0xe6
			"", //0xe7
			"", //0xe8
			"", //0xe9
			"12-MB L3 Cache, 24-way set associative, 64-byte line size", //0xea
			"18-MB L3 Cache, 24-way set associative, 64-byte line size", //0xeb
			"24-MB L3 Cache, 24-way set associative, 64-byte line size", //0xec
			"", //0xed
			"", //0xee
			"", //0xef
			"64-byte Prefetching", //0xf0
			"128-byte Prefetching", //0xf1
			"", //0xf2
			"", //0xf3
			"", //0xf4
			"", //0xf5
			"", //0xf6
			"", //0xf7
			"", //0xf8
			"", //0xf9
			"", //0xfa
			"", //0xfb
			"", //0xfc
			"", //0xfd
			"", //0xfe
			"", //0xff
			};
			
const char *brand_id[] = {
			"",//0x00
			"Intel(R) Celeron(R) Processor",//0x01
			"Intel(R) Pentium(R)III Processor",//0x02
			"Intel(R) Pentium(R)III Xeon Processor",//0x03
			"Intel(R) Pentium(R)III Processor",//0x04
			"",//0x05
			"Mobile Intel(R) Pentium(R)III Processor-M",//0x06
			"Mobile Intel(R) Celeron(R)III Processor",//0x07
			"Intel(R) Pentium(R)4 Processor",//0x08
			"Intel(R) Pentium(R)4 Processor",//0x09
			"Intel(R) Celeron(R) Processor",//0x0A
			"Intel(R) Xeon(R) Processor",//0x0B
			"Intel(R) Xeon(R) Processor MP",//0x0C
			"",//0X0D
			"Mobile Intel(R) Pentium(R)4 Processor-M",//0x0E
			"Mobile Intel(R) Celeron(R)Processor",//0x0F
			"",//0x10
			"Mobile Genuine Intel(R) Processor",//0x11
			"Intel(R) Celeron(R) M Processor",//0x12
			"Mobile Intel(R) Celeron(R) Processor",//0x13
			"Intel(R) Celeron(R) Processor",//0x14
			"Mobile Genuine Intel(R) Processor",//0x15
			"Intel(R) Pentium(R) M Processor",//0x16
			"Mobile Intel(R) Celeron(R)Processor",//0x17
			};
const char *brand_id_ex[] = {
			"",//0x00
			"",//0x01
			"",//0x02
			"Intel(R) Celeron(R) Processor",//0x03
			"",//0x04
			"",//0x05
			"",//0x06
			"",//0x07
			"Intel(R) Genuine Processor",//0x08
			"",//0x09
			"",//0x0a
			"Intel(R) Xeon(R) Processor MP",//0x0b
			"",//0x0c
			"",//0x0d
			"Intel(R) Xeon(R) Processor",//0x0e
			};
			
			
typedef	struct _STR_CPUID_VENDOR {
	int maximumFuncNumber;
	char vendor[13];
	}STR_CPUID_VENDOR;
	
typedef struct _STR_CPUID_BASEINFO{
	int processor_sig;
	int core_num;
	int brand_id;
	int stepping_id;
	int modul_number;
	int family_code;
	int type;
	int extended_model;
	int extended_family;
	int feature_flag_ecx;
	int feature_flag_edx;
	int fast_system_call;
	}STR_CPUID_BASEINFO;
	
typedef struct _STR_CPUID_CACHE{
	int descriptor_value_eax;
	int descriptor_value_ebx;
	int descriptor_value_ecx;
	int descriptor_value_edx;
	}STR_CPUID_CACHE;
	
typedef	struct _STR_CPUID_CACHE_PARAMETER{
	int apic;
	int maximun_threads;
	int full_associative;
	int self_initializing; // 0 or 1
	int cache_level;
	int cache_type;
	int associative_way;
	int physicaly_line_partion;
	int system_coherency_size;
	int num_of_sets;
	struct _STR_CPUID_CACHE_PARAMETER * next;
	}STR_CPUID_CACHE_PARAMETER;
	
typedef struct _STR_CPUID_MONITOR_NWAIT_PARAMETER{
	int smallest_minitor_line_size;
	int largest_monitor_line_size;
	int support_TIBE;
	int support_MBEx;
	int number_C7_C4;
	int number_C6_C3;
	int number_C2;
	int number_C1;
	int number_C0;
	}STR_CPUID_MONITOR_NWAIT_PARAMETER;

//cpuid.c
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "myCPUZ.h"

int canExcuteIns()
{
	//this function check wether your cpu support cpuid or not
	int a = 0;
	asm(
		"pushf\n\t"
		"popl		%%eax\n\t"
		"movl	%%eax,	%%ecx\n\t"
		"xorl		$0x200000,		%%eax\n\t"
		"pushl	%%eax\n\t"
		"popf\n\t"
		"pushf\n\t"
		"popl		%%eax\n\t"
		"test		%%eax,		%%ecx\n\t"
		"je		1f\n\t"
		"movl	$1,				%0\n\t"
		"jmp		2f\n\t"
		"1:\n\t"
		"movl	$0,				%0\n\t"
		"2:\n\t"
		:"=r"(a)
		:
		:"eax","ecx"
	);
	return a;
}

void GetCPUVendor(STR_CPUID_VENDOR *vendor)
{
	//before you use this function , define "char vendor[13]" in parant function
	int core_num;
	asm(
		"cpuid\n\t"
		"movl	%%ebx,	(%1)\n\t"
		"movl	%%edx,	4(%1)\n\t"
		"movl	%%ecx,	8(%1)\n\t"
		:"=a"(vendor->maximumFuncNumber)
		:"D"(vendor->vendor),"0"(0)
		:"ecx","edx"
	);
}
void GetCPUBaseInfo(STR_CPUID_BASEINFO *baseinfo)
{
	int org_info;
	int core_num;
	asm(
		"cpuid\n\t"
		:"=a"(org_info),"=b"(core_num),"=c"(baseinfo->feature_flag_ecx),"=d"(baseinfo->feature_flag_edx)
		:"0"(1)
		:
	);
	baseinfo->processor_sig = org_info;
	baseinfo->core_num = (core_num & 0xff0000) >> 16;
	baseinfo->brand_id = core_num & 0xff;
	baseinfo->stepping_id = (org_info & 0xf);
	baseinfo->modul_number = (org_info & 0xf0) >> 4;
	baseinfo->family_code = (org_info & 0xf00) >> 8;
	baseinfo->type = (org_info & 0x3000) >> 12;
	baseinfo->extended_model = (org_info & 0xf0000) >> 16;
	baseinfo->extended_family = (org_info & 0xff00000) >> 20;
	
	if((baseinfo->feature_flag_edx >> 10) & 0x01)
	{
		if((org_info & 0xfff3fff) < 0x633)
		{
			baseinfo->fast_system_call = 0;
		}
		else
		{
			baseinfo->fast_system_call = 1;
		}
	}

}

void GetCacheDescriptors(STR_CPUID_CACHE *cache)
{
	asm(
		"cpuid\n\t"
		:"=a"(cache->descriptor_value_eax),"=b"(cache->descriptor_value_ebx),"=c"(cache->descriptor_value_ecx),"=d"(cache->descriptor_value_edx)
		:"0"(2)
		);
}

void GetCacheParameter(STR_CPUID_CACHE_PARAMETER * cache_parameter_head)
{
	STR_CPUID_CACHE_PARAMETER *p = cache_parameter_head;
	p->next = NULL;
	int input = 0;
	int org_eax = 1, org_ebx, org_ecx, org_edx;
	while(org_eax)
	{
		asm(
			"cpuid\n\t"
			:"=a"(org_eax),"=b"(org_ebx),"=c"(org_ecx),"=d"(org_edx)
			:"0"(4),"c"(input)
			);
		if(org_eax & 0xf)
		{
			STR_CPUID_CACHE_PARAMETER *cache_parameter = (STR_CPUID_CACHE_PARAMETER *)calloc(1,sizeof(STR_CPUID_CACHE_PARAMETER));
			
			cache_parameter->apic = ((org_eax & 0xfc000000) >> 26) + 1;
			cache_parameter->maximun_threads = ((org_eax & 0x3ffc000) >> 14) + 1;
			cache_parameter->full_associative = (org_eax & 0x200) >> 9;
			cache_parameter->self_initializing = (org_eax & 0x100) >> 8;
			cache_parameter->cache_level = (org_eax & 0xe0) >> 5;
			cache_parameter->cache_type = org_eax & 0xf;
			cache_parameter->associative_way = ((org_ebx & 0xffc00000) >> 22) + 1;
			cache_parameter->physicaly_line_partion = ((org_ebx & 0x3ff000) >> 12) +1;
			cache_parameter->system_coherency_size = (org_ebx & 0xfff) +1;
			cache_parameter->num_of_sets = org_ecx + 1;
			
			p->next = cache_parameter;
			p = cache_parameter;
			p->next = NULL;
			++input;
			continue;
		}
		org_eax = 0;
	}
}

void GetMonitorNwaitParameter(STR_CPUID_MONITOR_NWAIT_PARAMETER * mn_parameter)
{
	int org_eax, org_ebx, org_ecx, org_edx;
	asm(
		"cpuid\n\t"
		:"=a"(org_eax),"=b"(org_ebx),"=c"(org_ecx),"=d"(org_edx)
		:"0"(5)
		:
		);
	mn_parameter->smallest_minitor_line_size = org_eax & 0xffff;
	mn_parameter->largest_monitor_line_size = org_ebx & 0xffff;
	mn_parameter->support_TIBE = org_ecx & 0x2;
	mn_parameter->support_MBEx = org_ecx & 0x1;
	mn_parameter->number_C7_C4 = ((org_edx & 0xf0000) >> 16);
	mn_parameter->number_C6_C3 = ((org_edx & 0xf000) >> 12);
	mn_parameter->number_C2 = ((org_edx & 0xf00) >> 8);
	mn_parameter->number_C1 = ((org_edx & 0xf0) >> 4);
	mn_parameter->number_C0 = org_edx & 0xf;
}

char * GetCPUName(char *name)
{
	int i = 0;
	asm(
		"movl	$0x80000002,	%%eax\n\t"
		"movl	$3,	%%ecx\n\t"
		"0:\n\t"
		"pushl	%%eax\n\t"
		"pushl	%%ecx\n\t"
		"cpuid\n\t"
		"movl	%%eax,	(%0,%1,8)\n\t"
		"movl	%%ebx,	4(%0,%1,8)\n\t"
		"movl	%%ecx,	8(%0,%1,8)\n\t"
		"movl	%%edx,	12(%0,%1,8)\n\t"
		"popl		%%ecx\n\t"
		"popl		%%eax\n\t"
		"incl		%%eax\n\t"
		"addl		$2,	%1\n\t"
		"loop 0b\n\t"
		:
		:"D"(name),"r"(i)
		:"eax","ebx","ecx","edx"
		);
	return name;
}

int main(void)
{
	int i,j;
	int* p_i;
	
	char brand_string[49] = {0};

	STR_CPUID_VENDOR *cpuid_vendor = (STR_CPUID_VENDOR *)calloc(1,sizeof(STR_CPUID_VENDOR));
	STR_CPUID_BASEINFO  *cpuid_baseinfo = (STR_CPUID_BASEINFO *)calloc(1,sizeof(STR_CPUID_BASEINFO));
	STR_CPUID_CACHE *cpuid_cache = (STR_CPUID_CACHE *)calloc(1,sizeof(STR_CPUID_CACHE));
	STR_CPUID_CACHE_PARAMETER *cpuid_cache_parameter_head  = (STR_CPUID_CACHE_PARAMETER *)calloc(1,sizeof(STR_CPUID_CACHE_PARAMETER));
	STR_CPUID_CACHE_PARAMETER *p = cpuid_cache_parameter_head;
	STR_CPUID_MONITOR_NWAIT_PARAMETER *cpuid_mn_parameter = (STR_CPUID_MONITOR_NWAIT_PARAMETER *)calloc(1,sizeof(STR_CPUID_MONITOR_NWAIT_PARAMETER));

	if(!canExcuteIns())
	{
		printf("Your CPU does't Support CPUID INS!\nPress Enter to Exit\n");
		getchar();
		return 1;
	}
	else
	{
		printf("Your CPU Support CPUID INS!");
		getchar();
	}
	puts("#################### CPU INFO #########################");
	
	//Get CPU Vendor 
	//memset(cpuid_vendor,0,sizeof(cpuid_vendor));
	GetCPUVendor(cpuid_vendor);
	printf("CPU Maximum func:\t\t%d\n",cpuid_vendor->maximumFuncNumber);
	printf("CPU Vendor:\t\t\t%s\n",cpuid_vendor->vendor);
	printf("CPU Name:\t\t\t%s\n",GetCPUName(brand_string));
	
	//Get CPU Base Info
	GetCPUBaseInfo(cpuid_baseinfo);
	printf("CPU ID\t\t\t\t%s\n",
		(cpuid_baseinfo->brand_id)?
			(((cpuid_baseinfo->processor_sig ==  0x6b1) || (cpuid_baseinfo->processor_sig ==  0xf13) )?
				brand_id_ex[cpuid_baseinfo->brand_id]:
				brand_id[cpuid_baseinfo->brand_id]):
			"NOT SUPPORT!");
	printf("CPU Number:\t\t\t%d\n",cpuid_baseinfo->core_num);
	printf("CPU Stepping ID\t\t\t%d\n",cpuid_baseinfo->stepping_id);
	printf("CPU Model Number\t\t%d\n",cpuid_baseinfo->modul_number);
	printf("CPU Family Code \t\t%d\n",cpuid_baseinfo->family_code);
	printf("CPU type \t\t\t%d\n",cpuid_baseinfo->type);
	printf("CPU Extended Model\t\t%d\n",cpuid_baseinfo->extended_model);
	printf("CPU Extended Family\t\t%d\n",cpuid_baseinfo->extended_family);
	printf("CPU Feature Flag\t\t");

	//Get CPU Feature Flag
	for(i = 0 ; i <  64; i++)
	{
		if((i<32)?((cpuid_baseinfo->feature_flag_ecx  >> i) & 0x1):((cpuid_baseinfo->feature_flag_edx  >> (i-32)) & 0x1))
		{
			printf("%s",feature_flag_names[i]);
		}
		(i%10== 0 && i !=0 )?printf("\n\t\t\t\t"):i;
	}
	
	//Fast system call
	__w("\n%s\t\t%s\n","CPU Fast System Call",cpuid_baseinfo->fast_system_call?"YES":"NO");
	
	//Get Cache Infomation
	GetCacheDescriptors(cpuid_cache);
	
	//analysis EAX register
	for(j = 0; j < 4; j++)
	{
		p_i = &(cpuid_cache->descriptor_value_eax) + j;
		for(i = 0; i < 4; i++)
		{
			printf("CPU Cache\t\t\t%s\n",descriptor_decode_values[(*p_i & (0xff << ( i << 3))) >> (i << 3)]);
		}
	}
	
	//Get Cache Paramemter
	GetCacheParameter(p);
	
	while(p->next)
	{
		p = p->next;
		puts(">>>>>>>>>>>>>>>>>CPU CACHE<<<<<<<<<<<<<<<<<<");
	
		__w("CPU APIC\t\t\t%d\n",p->apic);
		__w("CPU maximun_threads\t\t%d\n",p->maximun_threads);
		__w("CPU full_associative\t\t%d\n",p->full_associative);
		__w("CPU self_initializing\t\t%d\n",p->self_initializing);
		__w("CPU Cache cache_level\t\t%d\n",p->cache_level);
		__w("CPU Cache cache_type\t\t%s\t\n",cache_type[p->cache_type]);
		__w("CPU Cache associative_way\t%d\n",p->associative_way);
		__w("CPU physicaly_line_partion\t%d\n",p->physicaly_line_partion);
		__w("CPU Cache system_coherency_size\t%d\n",p->system_coherency_size);
		__w("CPU Cache num_of_sets\t\t%d\n",p->num_of_sets);
		__w("CPU Total Cache \t\t%d KB\n",(p->associative_way * p->physicaly_line_partion * p->system_coherency_size * p->num_of_sets)>>10);
		
	}
	
	//Get MN Parameter
	GetMonitorNwaitParameter(cpuid_mn_parameter);
	
	__w("CPU smallest_minitor_line_size\t%d BYTE\n",cpuid_mn_parameter->smallest_minitor_line_size);
	__w("CPU largest_monitor_line_size\t%d BYTE\n",cpuid_mn_parameter->largest_monitor_line_size);
	__w("CPU support_TIBE\t\t%s\n",cpuid_mn_parameter->support_TIBE?"YES":"NO");
	__w("CPU support_MBEx\t\t%s\n",cpuid_mn_parameter->support_MBEx?"YES":"NO");
	__w("CPU number_C7_C4\t\t%d\n",cpuid_mn_parameter->number_C7_C4);
	__w("CPU number_C6_C3\t\t%d\n",cpuid_mn_parameter->number_C6_C3);
	__w("CPU number_C2\t\t\t%d\n",cpuid_mn_parameter->number_C2);
	__w("CPU number_C1\t\t\t%d\n",cpuid_mn_parameter->number_C1);
	__w("CPU number_C0\t\t\t%d\n",cpuid_mn_parameter->number_C0);

	puts("\n#################### CPU INFO #########################");
	getchar();
	return 0;
}

先写这一部分，接下来弄界面的。用VC + MinGW