Linux启动汇编部分（三）__v6_setup

 1 /*
 2  *    __v6_setup
 3  *
 4  *    Initialise TLB, Caches, and MMU state ready to switch the MMU
 5  *    on.  Return in r0 the new CP15 C1 control register setting.
 6  *
 7  *    We automatically detect if we have a Harvard cache, and use the
 8  *    Harvard cache control instructions insead of the unified cache
 9  *    control instructions.
10  *
11  *    This should be able to cover all ARMv6 cores.
12  *
13  *    It is assumed that:
14  *    - cache type register is implemented
15  */
16 __v6_setup:
17 #ifdef CONFIG_SMP
18     ALT_SMP(mrc    p15, 0, r0, c1, c0, 1)                @ Enable SMP/nAMP mode
19     ALT_UP(nop)
20     orr    r0, r0, #0x20
21     ALT_SMP(mcr    p15, 0, r0, c1, c0, 1)
22     ALT_UP(nop)
23 #endif
24 
25     mov    r0, #0
26     mcr    p15, 0, r0, c7, c14, 0                        @ clean+invalidate D cache
27     mcr    p15, 0, r0, c7, c5, 0                         @ invalidate I cache
28     mcr    p15, 0, r0, c7, c15, 0                        @ clean+invalidate cache
29     mcr    p15, 0, r0, c7, c10, 4                        @ drain write buffer
30 #ifdef CONFIG_MMU
31     mcr    p15, 0, r0, c8, c7, 0                         @ invalidate I + D TLBs
32     mcr    p15, 0, r0, c2, c0, 2                         @ TTB control register
33     ALT_SMP(orr    r4, r4, #TTB_FLAGS_SMP)
34     ALT_UP(orr    r4, r4, #TTB_FLAGS_UP)
35     ALT_SMP(orr    r8, r8, #TTB_FLAGS_SMP)
36     ALT_UP(orr    r8, r8, #TTB_FLAGS_UP)
37     mcr    p15, 0, r8, c2, c0, 1                         @ load TTB1
38 #endif /* CONFIG_MMU */
39     adr    r5, v6_crval
40     ldmia    r5, {r5, r6}
41 #ifdef CONFIG_CPU_ENDIAN_BE8
42     orr    r6, r6, #1 << 25                              @ big-endian page tables
43 #endif
44     mrc    p15, 0, r0, c1, c0, 0                         @ read control register
45     bic    r0, r0, r5                                    @ clear bits them
46     orr    r0, r0, r6                                    @ set them
47 #ifdef CONFIG_ARM_ERRATA_364296
48     /*
49      * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
50      * corruption with hit-under-miss enabled). The conditional code below
51      * (setting the undocumented bit 31 in the auxiliary control register
52      * and the FI bit in the control register) disables hit-under-miss
53      * without putting the processor into full low interrupt latency mode.
54      */
55     ldr    r6, =0x4107b362                               @ id for ARM1136 r0p2
56     mrc    p15, 0, r5, c0, c0, 0                         @ get processor id
57     teq    r5, r6                                        @ check for the faulty core
58     mrceq    p15, 0, r5, c1, c0, 1                       @ load aux control reg
59     orreq    r5, r5, #(1 << 31)                          @ set the undocumented bit 31
60     mcreq    p15, 0, r5, c1, c0, 1                       @ write aux control reg
61     orreq    r0, r0, #(1 << 21)                          @ low interrupt latency configuration
62 #endif
63     mov    pc, lr                                        @ return to head.S:__ret
posted on 2013-08-27 21:39 choi87 阅读(528) 评论(0) 收藏举报