JLink后台烧录方式

方式一：

SEGGER J-Link Commander V9.10 (Compiled Jan 14 2026 11:36:46)
DLL version V9.10, compiled Jan 14 2026 11:35:51

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled May 7 2021 16:26:12
Hardware version: V9.10
J-Link uptime (since boot): N/A (Not supported by this model)
S/N: 597111111
License(s): GDB, RDI, FlashBP, FlashDL, JFlash
VTref=3.153V

Type "connect" to establish a target connection, '?' for help
J-Link>r
Target connection not established yet but required for command.
Please specify device / core. : FM33LG04X
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>s
Specify target interface speed [kHz]. : 4000 kHz
Speed>auto
Device "FM33LG04X" selected.

Connecting to target via SWD
Found SW-DP with ID 0x0BB11477
DPIDR: 0x0BB11477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770021, ADDR: 0x00000000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC300. Implementer code: 0x41 (ARM)
Unknown core, assuming Cortex-M0
Found Cortex-M0 r0p0, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB00D ???
[0][1]: E0001000 CID B105E00D PID 000BB00A DWT
[0][2]: E0002000 CID B105E00D PID 000BB00B FPB
Memory zones:
Zone: "Default" Description: Default access mode
Cortex-M0 identified.
Reset delay: 0 ms
Reset type: NORMAL (https://kb.segger.com/J-Link_Reset_Strategies)
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Failed to attach to CPU. Trying connect under reset.
Failed to power up DAP
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Failed to power up DAP
CPU could not be halted
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x0BB11477
DPIDR: 0x0BB11477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC300. Implementer code: 0x41 (ARM)
Unknown core, assuming Cortex-M0
Found Cortex-M0 r0p0, Little endian.
J-Link>loadfile "D:\Project\RadarModuleTestSystem.YiYuan\Bin\DownloadFile\AM100AA_F_1.20_1.015.010_FR_V01\SYSTEM.bin" 0x00000000
'loadfile': Performing implicit reset & halt of MCU.
Reset type: NORMAL (https://kb.segger.com/J-Link_Reset_Strategies)
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Failed to power up DAP
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Failed to power up DAP
CPU could not be halted
Reset: Core did not halt after reset, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x0BB11477
DPIDR: 0x0BB11477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC300. Implementer code: 0x41 (ARM)
Unknown core, assuming Cortex-M0
Found Cortex-M0 r0p0, Little endian.
Downloading file [D:\Project\RadarModuleTestSystem.YiYuan\Bin\DownloadFile\AM100AA_F_1.20_1.015.010_FR_V01\SYSTEM.bin]...
J-Link: Flash download: Bank 0 @ 0x00000000: Skipped. Contents already match
O.K.
J-Link>g
Memory map 'after startup completion point' is active
J-Link>

方式二：
"C:\Program Files\SEGGER\JLink_V910\JLink.exe" -device GD32F303CGT6 -if SWD -speed auto -autoconnect 1 -CommandFile D:\AUTO.jlink