摘要：ASIC worldhttp://asic.co.in/ASIC and VLSI Job Seekers Paradise welcomes youSystemVerilog.intestbench.inhttp://ratnendrapandey.com/asic_interview_questions/asic_questions.htmlhttp://www.asicguru.com/http://only-vlsi.blogspot.com/http://fullchipdesign.com/interview.htmhttp://www.angelfire.com/in/rajes 阅读全文

摘要：原文来自: eetop, link 下面这些问题和回答是基于我个人对验证（主要是动态仿真验证）的理解，可能有理解的不到位、理解有偏差的地方，欢迎大家指正。我是synopsys的用户，所以下面描述的大多是针对synopsys的工具。欢迎发邮件到lshj98115@sohu.com和我讨论验证的问题。Q：验证的目的？A：发现Bug，发现所有的Bug，或者证明没有Bug（转自夏晶的帖子）Q：对验证工程师的要求？Hacker mentality，Organized testing，Tool automation。 如何做更多的testcase、如何覆盖更多的测试点、如何充分的利用服务器、如何尽可能.. 阅读全文

摘要：A module and a program block carry many similarities.Similar to a module, a program block may have zero or more inputs, outputs and inout ports.A program block can contain zero or more initial blocks, cont assignments, generate and specparam statements, concurrent assertions and timunit declarations 阅读全文

摘要：NRZI diagram[2]First part is encoder, second part is decoder. Small modification is in the bit_stream sampling part.Some comments:1. use DFF to buffer the input2. use 1'b1 instead of 1, because during synthesis, 1 will be viewed as integer type:example, like adder, cnt + 1'b1; 1'b1 will 阅读全文

摘要：Author: RuiReference from the website and wikipediaSomething to mention:1.$display always to display the last sampled value,may cause some mismatch in the screen output2.parameterized module design help to scalingGrey encoder//greyencoder,frombinaryinputtogreyoutput//algorithm://fromrightmost,x[i]xo 阅读全文

摘要：1. 需要注意的是 nonconsecutive [=M:N]和 goto repetition[-> M:N]的区别例子(SVA handbook)a ##1 b[=2] ##1 c //a x x b x x x b x x c , then anytime later, c is turea ##1 b[->2] ##1 c //a x x b x x x b c, at next cycle, c is tureconsecutive range的例子a ##1 b[*1:5] ##1 c //a b b b b c 与上面的区别在于，所有的信号关系都是时钟连续的2. Pr 阅读全文