gold序列的verilog实现

gold序列产生程序：

 

module gold_sque_gen(
  rst,
  clk,
  delay,
  gold_out
  );

input rst;
input clk;
input [11:0] delay;
output reg gold_out;

reg [11:0] counter;
reg [11:0] m1_sequence;
reg [11:0] m2_sequence;
reg [1:0] state;

parameter ready = 2'b00;
parameter calcu = 2'b01;

always @(posedge clk)
begin
  if(!rst)
    begin
      m1_sequence <= 12'b1111_1111_1111;
 m2_sequence <= 12'b1111_1111_1111;
 gold_out <= 1'b0;
 state <= ready;
    end
  else
    begin
      case(state)
        ready:
          begin
            counter <= delay;
            state <= calcu;
          end 
        calcu:
          begin
            if(counter == 0)
              begin
                m1_sequence[11:1] <= m1_sequence[10:0];
                m1_sequence[0] <= m1_sequence[0]^m1_sequence[3]^m1_sequence[5]^m1_sequence[11];
                m2_sequence[11:1] <= m2_sequence[10:0];
                m2_sequence[0] <= m2_sequence[2]^m2_sequence[3]^m2_sequence[6]^m2_sequence[11];
                gold_out <= m1_sequence[11] ^ m2_sequence[11];
              end
            else
              begin
                counter <= counter - 12'd1;
 m1_sequence[11:1] <= m1_sequence[10:0];
                m1_sequence[0] <= m1_sequence[0]^m1_sequence[3]^m1_sequence[5]^m1_sequence[11];

              end
          end
        endcase
    end
end

endmodule

程序中m序列优选对分别为：f(x)=x^12+x^6+x^4+x+1            g(x)=x^12+x^7+x^4+x^3+1
程序中rst为同步复位信号，clk为时钟信号，delay为m2序列的延时信号，用于相位调整，延时器取不同值时产生的gold序列不同该发生器最多可以产生2^12=4096种不同序列，其中一半是平衡的。

其测试程序为：

`timescale 1 ns/100 ps
module gold_sque_gen_test;
  
reg clk;
reg rst;
reg [11:0] delay;
wire gold_out;

initial
begin
  rst = 0;
  clk = 0;
  delay = 12'b0000_0000_1111;
 #40
  rst = 1;
  
end

always #10 clk = ~clk;

gold_sque_gen gold1(
  .clk(clk),
  .rst(rst),
  .delay(delay),
  .gold_out(gold_out)
);

endmodule