作业

计数器的设计与实现

一、实验目的

计数器是实际中最为常用的时序电路模块之一，本实验的主要目的是掌握使用HDL描述计数器类型模块的基本方法。

二、实验仪器与器材

EDA开发软件、微机、实验开发系统、打印机、其他器件与材料。

三、实验说明

计数器时数字电路系统中最基本的功能模块之一，设计时可以采用原理图或HDL语言完成。下载验证时的计数时钟可选用连续或单脉冲，并用数码管显示计数值。

四、实验要求

   1. 设计一个带有计数允许输入端、复位输入端和仅为输出端的10进制计数器；

   2. 编制仿真测试文件，并进行功能仿真；

   3. 下载并验证计数器功能；

   4.为上述设计建立元件符号。

五、实验程序

（一）10进制计数器

A、实验程序设计

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity count_10 is port(

            rst,clk:in std_logic;

  

                  y:out std_logic_vector(6 downto 0)

                         );

 

end count_10 ;

 

architecture Behavioral of count_10  is

        signal count_1:STD_LOGIC_vector (3 DOWNTO 0);

        signal data_1:STD_LOGIC_vector (3 DOWNTO 0);

        signal outdata1:std_logic_vector(6 downto 0);

        

 

begin

 

count1: process(rst,clk)

 

begin

     if (rst='1') then

           count_1<="0000";  

     elsif (clk'event and clk='1') then

            if count_1="1001" then

             count_1<="0000";

            else count_1<=count_1+1;

            end if;

     end if;

  

 end process;

  

                                         

led1:process(rst,clk)

  

     begin

         if rst='1' then

            outdata1<="1000000";

         else  if (clk'event and clk='1')  then

            case count_1 is

                 WHEN "0000"=>outdata1<="1000000";

                 WHEN "0001"=>outdata1<="1111001";

                 WHEN "0010"=>outdata1<="0100100";

                 WHEN "0011"=>outdata1<="0110000";

                 WHEN "0100"=>outdata1<="0011001";

                 WHEN "0101"=>outdata1<="0010010";

                 WHEN "0110"=>outdata1<="0000010";

                 WHEN "0111"=>outdata1<="1111000";

                 WHEN "1000"=>outdata1<="0000000";

                 WHEN "1001"=>outdata1<="0010000";      

                 when others=>outdata1<="1000000";

            end case;

          end if;

         end if;

        end process;

       y<=outdata1;

 end architecture Behavioral;