09 2011 档案

摘要:http://hi.baidu.com/xinchao628/blog/item/07e7a088a063faa70f244417.htmlThe clock tree sinks are the synchronous points of a clock tree.astro clock tree synthesis identifies the following pins as clock tree sinks..sequential cells'clock port with trigger edge information.user-defined synchronous p 阅读全文
posted @ 2011-09-17 15:29 Hello Verilog 阅读(717) 评论(0) 推荐(0) 编辑
摘要:clock uncertaintyhttp://shunlang.blogbus.com/logs/71012206.html发现以前的理解有些错误,更正一下Pre CTS:Clock Uncertainty = Clock skew + Clock jitter + MarginPost CTS:Clock Uncertainty = Clock jitter + Margin Jitter is a quantitative measure for the clock uncertainty ,it's a really clock ,output of pll.oscClock 阅读全文
posted @ 2011-09-02 08:48 Hello Verilog 阅读(1515) 评论(0) 推荐(0) 编辑